Power Integrity Analysis in Your PCB Design Software

Power integrity problems can abound in modern PCBs, especially high-speed boards that run with fast edge rates. These systems require precise design of the PDN impedance to ensure stable power is always delivered throughout the system. Without carefully considering the PDN impedance, you’re at risk of creating ripple and noise in the power distribution network when fast signals switch states. As more signals switch in large ICs, the result is the potential for greater power instability and system disruptions during operation.

Some designers might wonder what is power integrity analysis: it’s a set of methods for understanding how your components draw power and how the structure of the board affects stable power delivery. Altium Designer offers some important tools for power integrity analysis, including the new Power Analyzer extension from Keysight. This article will give an overview on how to perform power integrity analysis in a PCB, as well as where to access these features in Altium Designer.

Power Integrity Challenges in DC and AC

Some products will operate at high voltage, high speed, high current, high frequency, or all of the above, and they can experience a range of signal integrity and power integrity problems during operation. Power integrity analysis aims to identify operation problems from two perspectives: DC and AC. Furthermore, power integrity analysis can be performed in two phases: in the schematic and in the PCB layout. Simulation experts are sometimes called in to evaluate a design prior to prototyping or production in order to identify potential power integrity problems in DC and AC domains.

Power integrity analysis involves analyzing the structure and electrical behavior of the PDN in a PCB. To be more specific, it involves calculating certain electrical quantities which can be indicative of power integrity problems. In particular, there are several quantities that can be calculated in the PDN using simulation tools, which can then be linked to certain power integrity problems that would be observed in a PCB during operation. Quantities to calculate include (but not limited to):

• PDN Z-parameters (self-impedance and transfer impedance) in AC and DC, or S-parameters
• DC resistance and current density in rails and planes
• Voltage and current distribution throughout the PCB layout
• Transient response on power rails observed in the time domain

These important mathematical quantities in power integrity analysis can be estimated in schematics using SPICE or IBIS models, or they can be calculated in the PCB using an electromagnetic field solver. After calculating the quantities of interest, they should be compared to target values to ensure compliance with your product specifications.

What Power Integrity Problems Can Occur in a PCB?

There are several power integrity problems that can occur in a PCB, all of which are related to the list of quantities listed above. Some of the common power integrity problems that can occur in a circuit board include:

• Large power rail collapse (ripple, seen as a transient response) and ground bounce
• Radiated emissions due to weak decoupling and ripple
• Noise coupling between different regions of a PCB
• Excessive power dissipation that produces heat

The goal in constructing a PDN is to ensure the power drawn into the components on a PCB is delivered with minimal instability. Some of the power integrity problems listed above are observed as signal integrity problems (specifically ground bounce) and EMI/EMC problems (noise coupling and emissions). The matrix below shows which power integrity problems are linked to the mathematical quantities listed above.

To learn more about these factors in a PDN and how they affect stability in power delivery, read the following resources to fully understand power integrity analysis.

• Learn more about power integrity simulation and analysis in our free Ebook

AC Power Integrity Simulation in Schematics

Schematics are a good place to start modeling AC power integrity before transitioning to the PCB layout. In this domain, it's possible to use SPICE simulations or IBIS-based simulations to model your decoupling strategy and determine whether your idealized PCB layout can support stable power delivery, particularly for fast digital integrated circuits.

Schematic-level power integrity does not account for the important physical factors in a PCB layout that will impact power integrity. Instead, investigating power integrity in schematics helps a designer develop design goals for the PDN to ensure power delivery will be as stable as possible. This requires modeling the PDN response using generic components to represent the physical aspects of the PCB layout. Some of these physical aspects include:

• Decoupling/bypass capacitor models, which includes ESR and ESL values
• Plane capacitance, which is typically on the order of pF
• Spreading inductance, or the inductance of the region where current exists in power/ground plane layers
• Via inductance, although this is normally included in the decoupling/bypass capacitor models
• Topology with multiple rails in the PDN
• A switching element that simulates a bitstream so that a periodic transient response can be observed

A relatively simple model that includes only RLC elements is shown in the example schematic sheet below. This example can be used to estimate PDN impedance and the inductive slope in the PDN impedance spectrum out to several hundred MHz. The model can also be used to directly visualize ripple on the PDN by running a transient analysis simulation.

The above series RLC circuit blocks are being used to model a decoupling capacitor network that might be placed in the board. The lower section shows the connections between the plane layers and a component package. Finally, the transistor is used with a pulsed source to model current drawn into the network. The current and voltage measurments at the output points can be used to determine the PDN impedance using Ohm's law.

Based on these results, it's possible to determine target values for your RLC elements in your SPICE model. The primary physical aspect this determines is the plane capacitance, as well as the number of decoupling capacitors. These values then become design targets in the PCB layout, and they will influence things like capacitor selection and stackup design.

There are two ways to evaluate power integrity from the above simulation model:

• In the time domain, by looking at the transient response on the PDN
• In the frequency domain, by looking at the impedance spectrum

The most common method for monitoring problems with AC power integrity in simulation and measurement is in the time domain. This is because AC PDN problems in a PCB are observed within the measurement range of moderately expensive oscilloscopes that are available in most labs or online. It is possible to take direct measurements of power rail ripple with a high input impedance probe, or to identify radiated emissions from excessive PDN ripple in the time domain. In both cases, the results can be examined on a graph of rail voltage vs. time, or equivalently rail current vs. time for current-controlled rails.

The graph below shows an example of simulation results illustrating the type of power rail fluctuations that could be observed in the time domain. The broad bandwidth of a digital signal is capable of exciting multiple poles in the PDN impedance spectrum, which then creates a complex multi-frequeny oscillation in the time domain.

When this kind of result is observed in the time domain, a corresponding measurement or simulation in the frequency domain can be used to determine the potential root cause. In the frequency domain, these measurements are difficult to access because the required piece of equipment (a vector network analyzer) is very expensive. However, these tools can be accessed at 3rd party labs, or the PDN impedance could be simulated in SPICE or a 3D field solver to determine the potential source of the problem.

The example below shows the corresponding impedance spectrum from the above simulation. The peaks in the impedance spectrum illustrate frequencies that could be targeted with decoupling capacitors, and the slope in the impedance spectrum going to very high frequencies shows the bandwidth limit that can be supported with the current PDN design. Higher bandwidth is normally supported on the device package, which can contain small-case discrete capacitors or internal ECMs that reduce PDN impedance in the GHz frequency range.

• Learn more about AC power integrity simulations in SPICE

PDN simulations also must occur in DC, both for high-speed digital designs and power system designs. In both cases, the PDN needs to  have enough copper to provide current to components without excess heating from resistive losses. These simulations rely heavily on the shape of copper in the power rails in the PCB layout, so they are typically performed with a 3D solver.

DC Power Integrity in the PCB Layout

The DC resistance in a circuit board depends on the dimensions of your power plane and interconnects, and it’s the starting point for understanding power integrity. Once this aspect of a circuit board is addressed, a designer can take steps to ensure they meet target impedance goals to prevent signal integrity problems that arise from unstable power delivery.

The newest power integrity analysis extension in Altium Designer is the Power Analyzer by Keysight. This utility can set up a power tree based on your netlist and project information. An example power tree is shown below.

Please note: The Power Analyzer extension currently only supports DC power integrity analysis. AC power integrity analysis is still under development.

DC power analysis starts in the PCB layout and requires setting up a simulation that maps power distribution throughout different power nets in the PCB layout. This is represented visually as a tree with different power levels, which maps power flow from a top-level input and down to the device level.

Once this power tree is set up, it can be used to determine the DC resistance in the PDN. The image below shows an example output from Power Analyzer in Altium Designer. This extension provides power integrity calculations inside the PCB Editor in Altium Designer, and the results are checked against design goals or constraints automatically. No additional analysis tools are needed to implement this calculation, and the results do not need to be checked manually against your design rules.

The results below shows DC current displayed as a heat map in a large trace leading between two vias. In particular, the tool shows that the calculated current in the attached vias is 1.785 A. Based on operational goals in the design and operating current limits defined in IPC standards, it is possible to determine whether any modification of the design is needed. After making modifications, the simulation can be immediately re-run and the results can be examined to determine when any of the identified problems have been solved.

If we zoom out from individual traces or rails, it's possible to see current distribution throughout a plane layer or along large interconnects. Multiple points on a power rail can be selected and examined for voltage drop or current density, all being visualized as a heatmap. This view provides a simple way to determine when the DC resistance of a net becomes too large or when there is a current bottleneck that produces a hotspot.

• To learn more about Power Analyzer by Keysight, read the technical documentation

Collaborative Design and Power Integrity Analysis

Keeping the PDN impedance low is important for ensuring high-speed components do not create power rail ripple and ground bounce when they switch. If the PDN impedance is low enough, then these effects will not be noticed in the system. Once the plane impedance in the PDN has been calculated, it’s now possible to determine whether any power rail ripple and noise will cause the power delivery to fall outside the allowed limits.

To help you succeed in power integrity analysis, the Power Analyzer by Keysight and the existing simulation tools in Altium Designer^® can help you get started evaluating your board's functionality. As new capabilities come available, expect more updates to the Power Analyzer extension, including AC power integrity analysis direclty in the PCB Editor. Keep an eye on the What's New page to keep track of all new feature releases in Altium Designer.

• Everything you need for design, manufacturing, layout, routing, and simulation is included in Altium Designer.

  Learn more about the unified design environment in Altium Designer.

• The Power Analyzer utility takes data directly from the Layer Stack Manager and from the PCB Editor to build powerful simulations and quickly gives designers insights to ensure power integrity.

  Learn more about the Power Analyzer utility in Altium Designer.

• When you’re ready to share your project with other PCB designers or your manufacturer, Altium 365 lets you instantly share your circuit board design and production data through Altium Designer or on the web.

  Learn more about sharing your PCB project data with Altium 365.

Altium is committed to continuously bringing you the best tools for power integrity analysis, all operating within schematic and the PCB layout. As these capabilities are built into the application, more advanced power integrity simulations will become accessible inside the PCB Editor. In addiiton to improvements in the PCB Editor, additional capabilities will be made available to collaborators through the Altium 365^™ platform.

We have only scratched the surface of what’s possible with Altium Designer on Altium 365. Start your free trial of Altium Designer + Altium 365 today.