Ferrite Bead Models and Transfer Impedance in a PDN Simulation

The use of ferrites in a PDN is one design recommendation that is fraught with unclear guidance and over-generalized recommendations. If you see an application note or a reference design that recommends placing a ferrite in a PDN, should you follow this in your specific design, or should you ignore this and focus on adding capacitance? What if you’re using the ferrite to isolate two rails?

These are two questions we want to answer in this article. There may be two typical uses of ferrites in a PDN: as a supposed filtering element connected directly to a VDD pin, or as a blocking element between two different rails. The first one case should be avoided, yet the 2nd case has shown some promise if the ferrite is chosen correctly and if used on the appropriate rail. This is something you can examine in a SPICE simulation in an intermediate frequency range (up to about 1 GHz), and it’s what I’ll look at in this article.

Ferrite Beads in a PDN: Filtering or Isolation?

I’ve stated many times, and other designers will agree, that placing a ferrite in a PDN will add inductance to a PDN at intermediate frequencies, which is generally a bad idea if the PDN needs to support components that switch at fast edge rates (about 1 ns or less). Plenty of data backs up this assertion, particularly when the ferrite is connected to a rail that supplies power to high speed I/Os. Still, this is something seen in application notes on power regulators generally, and the use of ferrites sometimes gets taken out of context or implemented where it doesn’t make sense.

That being said, I’ve designed boards without including a ferrite for isolation, even if the ferrite was recommended as part of the reference design or included in an application note. Another author on this blog backs up this assertion. This includes omitting the ferrite as an element to isolate one rail from another, such as the VDD input and a PLL power rail.

This case of using a ferrite as an isolating element between two rails on a PDN is what we want to look at in a SPICE simulation in this article. Essentially, we want to simulate the transfer impedance between two rails on a PDN. Read this article to learn more about transfer impedance before proceeding further, as well as this article looking at our basic PDN simulation with multiple caps. I’ll continue with the basic PDN simulation model by adding a rail and attempting to isolate it with a ferrite.

Simulation Model With a Ferrite Bead

The simulation model for our PDN with a ferrite includes two rails: a supply rail for I/Os, and an additional rail modeling a slower switching element such as a PLL. The PLL rail is being isolated from the I/O rail using a ferrite bead (sometimes called a ferrite chip). The goal of our simulation is to examine the effectiveness of a typical ferrite as an isolating element between these two rails.

The decoupling capacitor bank consists of 36 caps with various self resonant frequency (SRF) values as shown in a previous PDN simulation article.

The ferrite used in the simulation is part number BLM18PG121SN1 from Murata. This was modeled using a parallel RLC circuit as is typically used in SPICE simulations to represent ferrites. Using the bandwidth, the resistance at resonance, and the resonant frequency, the ferrite can be modeled by taking R = 150 Ohms, L = 347 nH, and 0.3603 pF. Note that this is not a perfect representation of the ferrite, but it is the best that can be done without a precise simulation model for this part.

During the simulation, we’ll modulate the R value of the ferrite just to see its effects on noise transfer between the two rails in the simulation model. With the earlier decap simulation model and the above model for the isolating ferrite on the PLL rail, we now have what we need to perform a simulation. We’ll examine a few cases to distinguish between different noise sources:

• The voltage at the PLL rail when only the I/O rail is switching
• The voltage at the PLL rail when the PLL is switching and the I/O is switching

Both cases allow us to calculate the PDN’s entire impedance matrix if we like. Since we have 2 rails, this would be a 2x2 matrix relating the current draw at port n to the voltage measured at port m:

Goal #1 above amounts to calculating Z21 in the impedance matrix. We’ll use this to help explain the results seen in the simulation. To examine noise propagation into the PLL rail, we’ll compare the PLL rail voltage waveform with the I/O rail voltage waveform.

Results: I/O Rail Switching, PLL Quiet

The initial results comparing the voltage on the I/O rail with the voltage on the PLL rail are shown below. The I/O rail is switching with 1 ns rise time at 1 MHz frequency, while the PLL rail is not switching.

The time-domain waveforms below seem to suggest the ferrite has no effect on noise isolation, regardless of the ferrite’s effective parallel resistance and inductance. In fact, increasing the ferrite’s inductance by a factor 1000 appears to have no effect on noise isolation.

While it is not obvious, there is a very sharp transition right on the rising edge of the I/O voltage waveform. If we zoom in, we can see that this rising edge is not an artifact, but rather it is associated with a high-frequency pole in the I/O rail’s impedance (in the Z11 parameter).

Now we can see the effect of the ferrite; there is high-frequency noise generated on the I/O rail due to a pole in the Z11 parameter located at 631 MHz. This same pole exists in the transfer impedance spectrum (Z21), but it happens to be at much lower impedance. However, the high-frequency portion of the transient response, as shown above, experiences greater damping thanks to the placement of the ferrite. It’s clear that the standard R/L value in the ferrite model is the factor that determines damping in the transient response, just as is the case in any other RLC circuit. In other words, we would prefer a large resistance and a low inductance, which runs counter to the justification for using a ferrite in a PDN.

In contrast, the low-frequency noise appears to be totally unaffected by the ferrite. The low-frequency noise at 2.81 MHz is nearly identical on both rails, so we would expect the Z-parameters for these rails and the Z21 spectrum to have the same poles at 2.81 MHz. Indeed, this is what we see in the Z-parameter spectra shown below.

From comparing the self-impedance of the I/O rail (Z11) with the transfer impedance spectra (Z21), it’s very clear that there is only marginal benefit at the 631 MHz pole and no benefit at the 2.81 MHz pole (this is the main pole that matters). While it might appear that the ferrite on the PLL rail is responsible for reducing the noise, the bypass capacitor also reduces the noise thanks to its SRF value at 1.59 GHz. The two together act similar to a controlled ESR capacitor, providing high damping and reduced noise.

Results: PLL Rail Switching, I/O Switching

Now we can investigate how switching on the PLL rail will be affected by the presence of the ferrite. The transient analysis results below clearly show how the switching action in the PLL creates huge glitches in the PLL rail voltage. The red and green curves show the PLL rail voltage with and without a ferrite, respectively. As soon as the PLL switches on after 5 us (blue dashed curve), we see that the PLL rail with the ferrite exhibits huge voltage spikes. These spikes are not seen on the same PLL rail with the ferrite removed.

We can clearly see that the PLL rail is clean again once we remove the ferrite (see the green curve above). In fact, we don’t even see the noise from the I/O section! This should be the nail in the coffin for the ferrite in this design; the bypass capacitor is the big reducer of noise, not the ferrite. The results confirm that more capacitance is a favorable design change rather than adding inductance. This also illustrates the required design change on the I/O rail: add some small capacitors that directly target the 631 MHz peak in the PDN impedance spectrum.

Summary

What have we learned from this exercise? The results seem mixed, giving minimally acceptable results for the high-frequency pole and no results for the more problematic low-frequency pole. There are four important points:

1. The ferrite blocked some high-frequency noise from the I/O rail from reaching the PLL rail. This was achieved because the pole was located in the ferrite's resistive band, which can be seen by comparing the I/O noise measured on the I/O rail vs. the I/O noise measured on the PLL rail.
2. The bypass capacitor on the PLL rail greatly aids isolation as long as this capacitor is chosen properly (such that its SRF is close to the high-frequency pole).
3. The ferrite did absolutely nothing to reduce the low-frequency noise from the I/O rail from reaching the PLL rail. If the PLL were running as low as 0.9 V, the low frequency noise would create significant interference.
4. When the simulated slow-edge PLL element was switching, the inductance of the ferrite caused very large spikes on the PLL rail.

Overall, it looks like the ferrite was not much help where it was needed. We can deduce that adding dutifully chosen capacitors would provide the same benefits as the ferrite without the additional problems that come with the ferrite. From the bead’s impedance curve, we can see that the bead provides practically zero additional damping at low frequency, so we would not expect the low-frequency noise to be attenuated. The low-frequency noise can instead be addressed by targeting it with a large capacitor that has SRF = 2.81 MHz on both rails.

So, should you use a ferrite for isolation in your PDN? Be careful with this as it depends on the range of frequencies you need to isolate against. In addition, you should check that the ferrite does not create a new noise problem on the isolated rail. If you think you need to use a ferrite for rail isolation in your PDN, make sure you simulate this first to ensure the ferrite accomplishes the intended purpose.

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