The above image shows a PCB with two large capacitors that might be used as the output caps for a VRM, which then can supply DC power to an integrated circuit. However, this board hides an important source of inductance: the power plane and power rails.

If you’re working with a high speed digital component, there are some simple power integrity rules that should be followed. Using plane pairs, decoupling capacitors, and bypass capacitors are the starting point for designing the PDN in your PCB to have the required impedance. There is one quantity that is sometimes ignored when building a PDN impedance simulation: the spreading inductance of your plane pair. This quantity plays a deceptively simple role in determining the inductance leading into the input power pin on a component.

All conductive elements in your PCB can have some parasitic elements, including plane pairs. The one that we normally care about is plane capacitance, which provides additional capacitance to help your PDN decouple at high frequencies. In a DC PDN simulation, we look at the DC conductivity to try and spot power loss. There is one additional parasitic in a plane pair: the spreading inductance.

Simply put, the spreading inductance is the inductance created by the current path drawn along two planes and the circuit elements that connect them. In the PDN of a PCB, the spreading inductance is defined by the current loop spanning from a decoupling capacitor network, along a power plane, into the load input, and back along the ground plane to the capacitor. It is not equivalent to the loop inductance formed by this current path, it is only the portion of total inductance contributed specifically by the plane. The various contributors to plane-pair impedance are shown below:

Why should we use the term “spreading inductance”? The term is used to denote that the current “spreads” in the power and ground plane pair, it does not follow a straight line. The current is confined to a narrow region between the decap output and the via input. Rather than following a literal straight line between these two points in the plane, current spreads out in the plane but does not totally fill copper in the plane pair.

This confinement of the current in the plane has an important consequence for PDN design: eventually, increasing the plane area does not necessarily decrease the spreading inductance. This is because, with a large plane, the current will not continue spreading along the current path. Instead, you can only change two other distances if you want to modify the spreading inductance as follows:

**Reduce d:**Bringing caps closer to the load IC reduces the spreading inductance**Reduce h:**Bringing the plane layers closer together reduces the spreading inductance

In general, linear time-invariant (LTI) electrical systems can be modeled as RLC circuits, and the same idea applies to a plane pair with spreading inductance. The image below shows how the spreading inductance along a power plane would be modeled in a schematic for use in a simulation. The portion of the plane connecting from C-Plane to OUT contains two elements: an inductance (L-Plane) and a resistance (R-Plane). L-Plane is our spreading inductance defined by the current loop formed in the PDN. Together with C-Plane, these three elements contain all parasitics related to a plane pair.

Technically, we would have additional elements along the GND net corresponding to the R-Plane value for the ground plane and an additional L-Plane element for the via connection, but we can lump this into the R-Plane/L-Plane elements if we like. What’s important is how connections would be made to other components in the above schematics. PWR is the output from the decoupling capacitor network. The series RL elements spanning from PWR to OUT model the location of the decoupling capacitor network.

Just as we indicated above, this means you have a simple way to reduce the spreading inductance: bring the decoupling capacitors closer to the input power pin on the load IC, or reduce the plane separation. In addition, you can use more vias to intentionally spread out the current in the power plane by placing vias connecting from a decap array to the power input in parallel. Alternatively, if you are using a large BGA component, just place the decaps directly on the back side of the board to minimize the spreading inductance.

What about decoupling capacitors that are connected to a plane pair? Does the spacing between the capacitors have some inductance? The answer is “yes” it does, but this inductance is easily reduced by placing the caps very close together. We should be able to see this above: placing the capacitors close to each other basically sets d = 0.

A good guideline to follow is to use the smallest case caps that can still hit your required capacitance specs. 0402 case size is a good general-purpose selection for high speed boards unless you’re designing to very high density and need 0201/01005 cases. In these caps, the ESR value will be non-negligible, which can actually be a good thing, and the ESL values tend to be lower.

Unfortunately, there is no closed form equation you can use to calculate spreading inductance. The calculation involves several integrals with an eigenfunction expansion. The fastest way is to export your design into a field solver application. If you want to learn more, there is one comprehensive resource found in the research literature:

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