PDN Impedance Simulation and Analysis in SPICE
Table of Contents
High speed signal behavior, RF signal propagation, and PDN simulations are some of the most difficult aspects of a PCB to simulate. Among these electromagnetic phenomena, high speed signal propagation and RF propagation require electromagnetic field solver tools to extract useful results. There are simply too many parasitics and design-specific effects to account for in a circuit simulation. Try as we might, there is just too much information to attempt to model in these two situations.
PDN simulations are a bit different as the relevant frequency range to be simulated is lower, typically less than 10 GHz for most devices. This means that a PDN supporting moderate speed digital components on a relatively small board can be modeled using SPICE simulations rather than full electromagnetic field solver simulations. As long as the board is small enough or frequencies are low enough that propagation can be ignored, you can get some useful results with a SPICE simulation.
If you’ve never done this before, I’ll show how to set this up and what kinds of results you might expect. By simulating switching action in a load component connected to a PDN, you can extract some useful data to describe your PDN and even calculate its network parameters. In the simulations I’ll show below, the goal is to extract:
- A PDN impedance spectrum
- The transient response as measured at the input pin of the load component
- How these parameters change as the amount of capacitance changes
The limitation to relatively low-speed and small boards is important, and I’ll describe a bit more what this really means as we proceed.
A standard simulation used to describe PDN impedance and calculate the transient response is shown in the schematic below. I’ve placed this in the Altium 365 Viewer so that users can browse through the design and see how the simulation is set up.
The simulation schematic was created with a set of decoupling capacitors that were not chosen in any particular order. I’ve kept the number low initially, but I’ll increase this later in the simulation just so we can see how increasing the capacitance affects the results. We’ll adjust the other parameters as well as we proceed.
This schematic is set up using components in the Simulation Generic Components library that is built into Altium Designer. If you’re not an Altium Designer user, you could certainly recreate this in any other simulation program using generic components in a SPICE package or another schematic editor. The overall simulation consists of four sections as I’ve indicated in the schematic:
- Regulator: This is the voltage regulator module or circuit that supplies power to the PDN. I’ve included its nominal output resistance and inductance.
- Decaps: This is the decoupling capacitor section. The capacitors have ESL and ESR included as discrete components just to show them clearly. Note that you could also define these values as parameters in these components inside the Properties Panel.
- Plane: This section defines the capacitance, inductance, and resistance of our power/ground plane pair. The inductance in this section is a spreading inductance, which I’ve described in another article.
- PWR_IN: This is the input power section in our load IC. I’ve attempted to model the input via inductance, pin-package inductance, and contact resistance at the input. These values are product and package specific, but the values here are typical order-of-magnitude numbers.
This equivalent circuit model requires adjusting the plane capacitance (CP1), plane inductance (LP1), and number of decoupling capacitors. We’ll use the transient analysis and AC sweep simulations to get these data. Before that, we should discuss the NMOS component shown above.
The PWR_IN section includes a model for the load, which is just a switching n-channel MOSFET. When modeling the load and looking at the transient response on the PDN, the goal is to examine how the PDN reacts to switching action, which then draws in current. Using a fast MOSFET in this way is one method to examine how the load current suddenly switches to a high current state based on some logic input. That logic input is modeled with the VSRC element set to Pulse mode in the Properties Panel. I’ve set the rise and fall times to 1 ns. This is not in the super high frequency range, although the 1/(rise time) bandwidth is 500 MHz, so the signal could be affected by poor decoupling in the planes and larger capacitors.
The other way to do this is with a current source set to pulsed mode. This would effectively perform the same function of switching the load between low and high current states. The simulation will then read the resulting current and voltage given to the MOSFET drain. A more accurate method would be to place a CMOS buffer circuit to model an IO, but that would be better for examining something like ground bounce or jitter, so we’ll save that for later. For now, we’ll look at the above model to examine what happens when logic circuits switch states and draw current through the PDN.
First, I want to look at the results for the above case, where we have 9 decoupling capacitors of various values in parallel, all with similar ESL and moderate ESR values. The ESR value is important here as it helps flatten out the PDN impedance spectrum, as I showed in another article on PDN impedance. The simulation parameters are as follows:
- Transient analysis: 10 ns step size, 5-10 us total simulation time
- AC sweep: 10 GHz maximum frequency, calculating |Z| for the PDN
- Decoupling capacitor number: I’ll look at the above block of 9 capacitors and a quadrupled block of 36 capacitors.
- Plane capacitance: Low state (CP1 = 20 pF) and high state (CP1 = 1 nF)
- Core voltage: VDD = 1.8 V
With only 9 decoupling capacitors and 20 pF plane capacitance, we can see very large fluctuations in the transient response reaching ~300 mV in amplitude superimposed on the desired 1.8 V core voltage. This is unacceptably large for any practical application and would produce large glitches on the output. The data shown here were extracted from the .sdf file and exported into Excel format.
Let’s see what happens when we quadruple the number decoupling capacitors and increase the plane capacitance by a factor 50. The new-and-improved version of this design is shown below. The decoupling capacitor block is basically copied to increase the equivalent capacitance of this decoupling network.
The results clearly show the benefit of having power/ground plane pairs and more decoupling capacitors; as the capacitance goes up, the amplitude of the transient response generally goes down, just like we would expect. The power rail response on the PDN fluctuates with only 100 mV amplitude when we quadruple the number of capacitors and increase the plane capacitance.
This is still a bit large for a 1.8 V rail, and it might seem that the use of 36 caps should produce a better result. We can get a sense as to why we don’t get significant damping with more capacitors by looking at the impedance spectra in each case.
We can also get the PDN impedance by taking the ratio of the complex V/I response functions in the frequency domain (AC sweep results), followed by calculating the magnitude of this ratio. We can see that the PDN impedance is still a bit large, particularly in the neighborhood of the 1/(rise time) bandwidth limit. We can also see the benefit when looking at the PDN impedance spectrum, as shown below. The graph below compares the current situation with 36 decaps/1 nF with the previous situation of 9 decaps/20 pF.
Note that we only have low impedance (100 mOhms) over about 1 decade. We’d like this band of low impedance to be lower and broader. We also have some peaks around 3 MHz and a high frequency response at 630 MHz. To solve these problems, we may need a greater number and diversity of capacitors. We can use some other tricks like increasing via count during the layer transition into the IC as this would reduce total inductance at PWR_IN input stage, and we could reflect this in the SPICE simulation.
Practically, having 36 low-ESL/low-ESR capacitors is common in high IO count ICs, and certainly in ICs that will draw 720 mA of current in a single pulse. In fact if you look at some reference designs or evaluation products that use high speed components with high IO count, you would find that 36 decoupling capacitors is a low number. Just for perspective, the dI/dt value for this pulse is 720 MA/sec (that’s 720 mega-Amperes per second!), which is a huge number requiring many capacitors to discharge very quickly. Embedded capacitance materials on this thin plane separation dielectric will also increase the plane capacitance.
What exactly qualifies as a “small” PDN? Remember, when the load switches, a broadband current pulse is pulled into the PDN, and this pulse travels along the PDN at the speed of light. Think of it as a propagating signal, but one that carries power instead of data. In the limit of a small PDN, we can ignore propagation effects just like we would in a transmission line. In fact, the transmission line comparison is apt here and a PDN is sometimes described with the same lumped circuit model used in transmission lines.
When the wavelength with the largest frequency component in the delivered power pulse is much larger than the nominal board size, we can ignore the fact that our delivered power has to propagate from the regulator output to the load input. This is the same logic used to understand why we can define a critical length in a transmission line. Once the design gets too large, or when the relevant bandwidth get to very high frequencies, electromagnetic solvers will be needed to run a complete PDN impedance simulation and extract the transient response.
The astute design engineer should notice something important: we haven’t included dissipation in the plane capacitance! This references the imaginary part of the dielectric constant, which would be modeled by adding some resistance in series with the plane capacitance. It basically plays the same role as G in the impedance equation for a transmission line. The size of this resistance requires some additional calculation, which will depend on the amount of loss in the dielectric material separating the plane layer. In the next article on power plane resonances, we’ll be able to see the beneficial effects of high loss tangent in the laminate.
There are two other points you should note for the load model in the schematics:
- Load capacitance on that input pin was not specified
- The FET capacitances were not specified and these would need to be set to a proper value
- If this PDN were providing power for an I/O bank, then we need to include its output transmission line and capacitive load in the simulation
- Any characteristics of the packaging PDN, such as discrete capacitors or the internal structure of the load component's substrate/interposer/die stack
- Inductive connections back to the ground plane, which are responsible for ground bounce
To see what this expansion on the simulation would look like, take a look at the image below. This schematic shows an example of a driver that toggles a CMOS buffer configured as a voltage follower; this is a basic model for a CMOS I/O buffer that would source a high-speed signal onto a trace in a PCB. The region in the red box is inside the chip and package of the load component.
There are several parameters in the above system:
- Cpin = load capacitance seen at the input pin
- Lp, Rp = inductance and resistance of the package interconnect between the pin and die
- LGND = inductance in the ground connection, such as through a via
- CLOAD = the load capacitance of the driven component
- T1 = the transmission line being driven by the Q2/Q3 buffer
In the above image, the load capacitance is applied as a discrete capacitor, but it only represents the capacitance on the input buffer pin. The FET terminal capacitances are not placed as discrete parts because they are built into the FET model as parameters. With modern CMOS architecture being physically smaller (now sub-10 nm), these capacitances can be very small. There could be other Cpin-type capacitances around the package before the CMOS buffer, which depends on the structure of the substrate, and routing in the RDL/interposer. Finally, the two pairs of probes would be used to provide a comparison between noise and the power rail and noise that gets injected into the output signal.
Obviously, there are many possible circuit elements to include in these types of simulations, and we have not even covered in-package and on-chip power integrity. Those portions of a package are designed to ensure power integrity at much higher frequencies, reaching into the GHz range.
The results shown above clearly show how adding capacitance decreases PDN impedance and helps stabilize the core voltage. The above caps were just selected a bit randomly, they weren’t based on a thorough analysis of targeting specific frequency ranges. We could get better results if we went through that exercise and produced a PDN impedance reduction over a broader bandwidth.
Some other points we could simulate in SPICE include:
- S-parameters for the PDN by calculating the impedance at the input and output ports, which we’ve already done
- Impulse responses for any current pulse pulled into the PDN
- Transfer impedances between multiple rails in the PDN
- The effects of additional inductance, such as adding a ferrite to the power pin; we’ll look at this in an upcoming article
- Addition of a bypass capacitor directly to the power input on the load (in parallel with Q1)
The built-in SPICE package in Altium Designer® can help you perform a range of simulations, including PDN simulations. When you’re ready to release these files to your collaborators for more advanced simulations, the Altium 365™ platform makes it easy to collaborate and share your projects. Everything you need to design and produce advanced electronics can be found in one software package.
We have only scratched the surface of what is possible to do with Altium Designer on Altium 365. Start your free trial of Altium Designer + Altium 365 today.