SAP (Semi-Additive PCB Process) – Burning Questions
In a previous blog post, we took a 10,000 foot view and went through a basic introduction to SAP. This Semi-Additive Process is an additional tool in the PCB fabricators toolbox that enables them to provide features sizes for trace width and spacing that are 25 micron, (1 mil) and below depending on the fabricators imaging equipment. We have been hearing about mSAP, or modified semi-additive process, for quite a while now, it is the technology driving many smart phone applications. There are a small number of facilities that are running this at very high volume. I think it is exciting to now have a semi-additive process that is able to support low volume, high mix applications.
As with all new technologies, PCB designers can expect to work through a learning curve with initial designs. This is not unlike the learning curve when working with flexible circuit designs, rigid flex designs and new materials. In an effort to help shorten that learning curve and at the same time stir up additional questions for us to tackle, I would like to share some of the common “first” questions I am often asked.
How does SAP work?
This question is often the first question when someone is being introduced to the concept of using 25-micron trace and space in their designs. Let’s contrast that with the well known subtractive etch process. With subtractive etch techniques, the fabricator starts with copper clad laminate and through a series of chemical and photolithography steps removes the copper not needed to create the circuit pattern. This process is typically “etch limited”, meaning that the etching process hits a pretty firm limit at 75-micron (3 mil) line and space. Below that, yields and reliability become much more challenging.
Semi-additive processes, as the name implies, adds copper to the dielectric layer rather than subtracting the copper. There are two primary versions of this, A-SAP™ and mSAP. The mSAP process starts with a layer of thin copper foil across the full panel, often 2-5 microns and the A-SAP™ technology enables the fabricator to remove all of the copper from the dielectric and then activate the panel to create a very thin layer of electroless copper, typically about .2 microns of copper. We will dive into the significance of that difference in copper thickness in a future blog.
Once this base copper is in place, the fabricator will use standard photolithography techniques to create the circuit pattern and then electrolytically plate the circuit traces. The resist is then removed, and the final step is to flash etch the remaining copper across the panel. From this step forward, the manufacturing panel is run through the remaining fabrications processes.
The key to SAP is the ultra-thin copper layer to start and the thinner the starting copper, the finer feature sizes a manufacturer will be able to support. The semi-additive processes now shift a fabricators capability from being etch limited to photolithography limited.
Can the SAP process and the subtractive etch process be used on the same layer?
Once the process itself is understood and designers start to think through how to apply this new opportunity to design with much finer trace and space, a common question is whether this SAP process can be used on a subtractive etch layer. The idea is often to apply very fine features in one are of the panel while using subtractive etch processing for the area that doesn’t need the fine pitch. This is an interesting concept and something that may be an option in a lab environment. In practice, I would not recommend this, and PCB fabricators will thank me for that!
There are a few ways to look at this interesting idea. First, it is common for SAP layers to be used in the same stack up as subtractive etch layers. SAP can be applied to printed circuit board layers with routing density challenges and PCB layers for power and ground can remain subtractive etch. This is a common and recommended approach.
We often talk about SAP and the ability to produce much smaller circuit trace and space. I also want to point out that SAP processes are not limited to these fine feature sizes. SAP can produce much larger circuit patterns as well. As a thought-starter, it is common for a design to have SAP layers that neck down to 25-micron line and space to improve routing density in a tight BGA area and then neck out a larger traces size once through that area. This helps minimize any impact on impedance control. As an added bonus, related to impedance control, the SAP process, because it is additive and not subtractive has much tighter control of line widths. Those larger traces, built with SAP, will have much less variance in width and consequently, much tighter impedance control that we are used to with subtractive etch printed circuit processing.
We will continue answering these frequently asked questions in upcoming blogs. Please reach out if there are burning questions you would like to have included!