Thermal Relief Via Design for Proper Impedance

Following DFM guidelines is a critical requirement for ensuring high yields and defect-free boards during fabrication. Most DFM guidelines are well-grounded and do not generally interfere with signal integrity. In the event that they do, most EDA tools include features that can help ensure you won’t sacrifice signal integrity for manufacturability, and the two design aspects often go hand-in-hand. One aspect of routing/layout, signal integrity, and manufacturability is the use of thermal relief vias.

Any via on an interconnect or connected to a plane layer has the potential to appear as an impedance discontinuity. The same applies to thermal relief via design. The impedance of both structures depends on their geometry, and placing a thermal relief via in place of a regular through-hole may impact impedance in different frequency ranges. Placing a thermal relief via with the proper geometry can help ensure signal integrity and manufacturability simultaneously.

Balancing Thermal Relief Via Impedance and Manufacturability

Just like via pad/anti-pad geometries have some particular impedance spectrum, so do thermal relief vias. It is quite important to design these structures to provide consistent impedance within your signal bandwidth. Like any conductive structure, the impedance can be capacitive or inductive in different frequency ranges. In addition, one should examine how the use of thermal relief vias differs from regular vias. As we’ll see, the contribution to impedance is more important below 1 GHz, but it will be less important at much higher frequencies.

Structure Determines Changes to Via Impedance

Changing the pad structure will change the parasitics surrounding the via, and thus we would expect some change in the via impedance. Indeed, there is a change in the via impedance when a thermal relief is placed on a via. However, the important question is whether this change in impedance matters in situations where we need to consider via impedance. The typical instance where we need to consider thermal relief contribution to via impedance is in a PDN because this is where components could connect back to large planes. The image below shows how the geometric parameters of a thermal relief on a via pad will affect parasitics.

Each of these factors can contribute to impedance; this is a mathematical fact. However, that impedance change may be very small or it may not participate in the PDN response. As we'll see below, at lower frequencies where the via characteristics matter, thermal relief vias do not have a major effect on via impedance. As I've outlined in another article (see the following link), other factors will be the major determinants of via impedance, and this will only really matter at higher frequecies.

• Learn more about via impedance.

Mid-range Frequencies (up to ~100 MHz to ~1 GHz) in a PDN

A recent paper on this topic looked at the impedance of thermal relief vias out to ~1 GHz using thermal relief via inductance to calculate the impedance. The authors fit parameters in a model to numerical simulations, providing an approximation of the inductance alone. At these relatively low frequencies, the impedance of thermal relief structures was found to be primarily inductive, meaning parasitic capacitance along the void in a thermal relief structure did not significantly contribute to the impedance.

At frequencies up to ~1 GHz, adding up to 4 thermal reliefs to a set of decoupling capacitors did not have an appreciable effect on the impedance of the network. The results from the group are shown below.

The above results look at mid-range frequencies, where you would really care most about PDN impedance (that is the specific case being examined). As can be seen, the impedance only has minor variations at ~10 MHz and ~150 MHz when a single thermal relief via is used. Two thermal relief vias in the decoupling network appeared to be the optimum number in this system. The question of adding thermal vias to a plane is one of determining whether they affect the impednace and capacitance along those connections.

We can see that the modification to the pads does not appear to significantly change the inductance of a decap's ESL value, so the via inductance still dominates the capacitor's overall response. One could say from the case of the four capacitors that the thermal relief pad removes some capacitance. This should be clear from the solid blue line, which has its resonances shifted to slightly higher frequencies. From these results, it appears that concerns regarding thermal relief via impedance at low frequencies, where there will be a lot of power being drawn from a plane pair into componets, are unfounded.

At Higher Frequencies (>1 GHz) in a PDN

At higher frequencies, how a thermal relief via affects impedance remains something of an open question. Based on the results above, we can see that the frequency range in the impedance plot only gets up to ~100 MHz; beyond that some study or simulation may be needed. I think there are two reasons for this:

1. At these frequencies, standard decaps will not be supplying the majority of power
2. These frequencies matter a lot more for signal vias rather than decap vias

The first reason has to do with the structure of a PDN and integrated circuits, and how these determine the PDN response to draws of current. Typical decaps have lower self-resonant frequencies (SRF) because their ESL can be overwhelmed by the via impedance along the connection to the power and ground plane, which is on the order of nH. At frequencies ~1 GHz and higher, the PDN response is dominated by the on-die capacitance and the plane capacitance. These two factors will dominate to determine the PDN impedance for two reasons: they have low inductance and moderate to low capacitance, so their SRFs are higher. Because the plane and die capacitance SRFs are higher, they will have lower impedance than typical decaps somewhere in the GHz range and will dominate power delivery, especially in high-speed PCBs.

In fact, this is justified by the graph shown above. At frequencies above 300 MHz, all the curves for the various numbers of thermal reliefs overlap, illustrating that the thermal reliefs on vias do not have a measurable contribution to the PDN impedance. For further comparison, the graph below outlines frequency ranges where different components of a PDN will dominate to determine the PDN impedance. I think this nicely illustrates why we care less about the response of vias with thermal reliefs at higher frequencies.

• Learn more about analyzing the PDN impedance in our free Ebook.

What About RF Power Delivery?

An exception here is in RF systems that may need to source power at very high frequencies, such as when an amplifier is being used into the GHz range (well above WiFi). In these systems, where caps need to supply power at high frequencies, there are very low ESL MLCC capacitors that can operate reliably up to very high frequencies. However, these tend to have capacitance on the order of 1 pF or less, so multiples are needed in parallel to provide a lot of power. This is another example where, if these very small capacitors are not present, the plane capacitance will dominate power delivery, particularly when there is larger separation between the two planes.

What About Signal Vias?

The other reason we don't really care about thermal relief impedance on vias at very high frequencies is because these are not used on signal vias. In addition, if you read the via impedance calculator article I linked above, you'll see that via impedance does not matter until you get above approximately 3 GHz. Below that, most via designs will be close enough to 50 Ohms anyways, and they will appear nearly invisible to a signal crossing the via.

The impedance of a via becomes quite important with very fast rise times (e.g., 10’s of ps) and can act like its own transmission line section when the vias are sufficiently long because the signal bandwidths are definitely reaching above the ~3 GHz limit. If fopr whatever reason, you must put a thermal relief on one of these signal vias, then looking from ~1 GHz to ~100 GHz with a field solver would allow you to examine the influence of parasitics capacitance on a thermal relief via's impedance. One would suspect that this causes thermal via impedance to switch from inductive to capacitive or vice versa depending on the number of nearby stitching vias.

The PCB layout and routing features in Altium Designer® make it unbelievably easy to design thermal vias with a simple utility. You can edit via properties from a single panel inside the PCB Editor, and you can create padstack templates that can be easily placed around the PCB. When you’ve finished your design, and you want to release files to your manufacturer, the Altium 365™ platform makes it easy to collaborate and share your projects.

We have only scratched the surface of what’s possible with Altium Designer on Altium 365. Start your free trial of Altium Designer + Altium 365 today.