Thermal Relief Via Design for Proper Impedance

Zachariah Peterson
|  Created: April 6, 2020  |  Updated: October 14, 2020
Thermal Relief Via Design for Proper Impedance

Following DFM guidelines is a critical requirement for ensuring high yields and defect-free boards during fabrication. Most DFM guidelines are well-grounded and do not generally interfere with signal integrity. In the event that they do, most EDA tools include features that can help ensure you won’t sacrifice signal integrity for manufacturability, and the two design aspects often go hand-in-hand. One aspect of routing, signal integrity, and manufacturability is the use of thermal relief vias.

Any via on an interconnect or connected to a plane layer has the potential to appear as an impedance discontinuity. The same applies to thermal relief via design. The impedance of both structures depends on their geometry, and placing a thermal relief via in place of a regular through-hole may impact impedance in different frequency ranges. Placing a thermal relief via with the proper geometry can help ensure signal integrity and manufacturability simultaneously.

Balancing Thermal Relief Via Impedance and Manufacturability

Just like via pad/anti-pad geometries have some particular impedance spectrum, so do thermal relief vias. It is quite important to design these structures to provide consistent impedance within your signal bandwidth. Like any conductive structure, the impedance can be capacitive or inductive in different frequency ranges. In addition, one should examine how the use of thermal relief vias differs from regular vias. As we’ll see, the contribution to impedance is less important below 1 GHz, but it may become much more important at much higher frequencies.

Mid-range Frequencies (up to ~1 GHz)

A recent paper on this topic looked at the impedance of thermal relief vias out to ~1 GHz using thermal relief via inductance to calculate the impedance. The authors fit parameters in a model to numerical simulations, providing an approximation of the inductance alone. At these relatively low frequencies, the impedance of thermal relief structures was found to be primarily inductive, meaning parasitic capacitance along the void in a thermal relief structure did not contribute to the impedance.

At frequencies up to ~1 GHz, adding up to 4 thermal reliefs to a set of decoupling capacitors did not have an appreciable effect on the impedance of the network. The results from the group are shown below.

Thermal relief via impedance simulation
Thermal relief via simulation data and impedance results. Image Source.

As can be seen, the impedance only has minor variations at ~10 MHz and ~150 MHz when a single thermal relief via is used. Two thermal relief vias in the decoupling network appeared to be the optimum number in this system. From these results, it appears that concerns regarding thermal relief via impedance at low frequencies are unfounded.

The impedance of a via becomes quite important with very fast rise times (e.g., 10’s of ps) and can act like its own transmission line section when the vias are sufficiently long (greater than 0.85 mm for a 20 ps rise time signal). This will not always be realized in every design, especially as baseband chips will force you to work in the HDI regime with short blind/buried vias. However, at higher frequencies, the impedance of these structures is still something to be considered for a number of reasons.

Higher Frequencies

At higher frequencies, how a thermal relief via affects impedance remains something of an open question. A prime example where via geometry becomes a critical factor in signal integrity is in the mmWave regime, where the wrong via geometry can incur excessive insertion loss on an interconnect.

Looking from ~1 GHz to ~100 GHz with an integrated field solver would allow designers to examine the influence of parasitic capacitance at the edge of a thermal relief via. One would suspect that this causes thermal via impedance to switch from inductive to capacitive, or to some complex mix of resonances/anti-resonances in the impedance spectrum. Obviously, this is quite difficult to predict from a circuit model.

Thermal relief via structure geometry and impedance
Effects of thermal relief via geometry on impedance contributions

How an Integrated 3D Field Solver Aids Routing

As the impedance of a thermal relief via primarily depends on the frequency and geometry of a signal, it becomes important to properly design these structures at high frequencies. Analytical expressions can only go so far as it is difficult to account for every possible parasitic in a circuit model. Therefore, a 3D electromagnetic field solver is the best choice for examining signal behavior at high frequencies.

An 3D field solver integrated into your routing tools does more than just aid thermal relief design. An integrated 3D field solver will also check your signal integrity requirements against your design rules. Some examples include impedance variations along an interconnect, delay tuning, and transient signal behavior. The great thing about this type of tool is you don’t have to export your board into a different application; it’s accessed automatically as part of a DRC or simulation.

With the high-quality CAD and routing tools in Altium Designer®, you can design any structure imaginable and place it in your layout, including a customized thermal relief via. The stackup manager also allows you to easily define layer transitions and build your board from standard stackup materials. You’ll have all the tools you need to build a cutting-edge layout, define manufacturing and assembly requirements, and prepare your new design for full-scale production.

Now you can download a free trial of Altium Designer and learn more about the industry’s best layout, simulation, and production planning tools. Talk to an Altium expert today to learn more.

About Author

About Author

Zachariah Peterson has an extensive technical background in academia and industry. He currently provides research, design, and marketing services to companies in the electronics industry. Prior to working in the PCB industry, he taught at Portland State University and conducted research on random laser theory, materials, and stability. His background in scientific research spans topics in nanoparticle lasers, electronic and optoelectronic semiconductor devices, environmental sensors, and stochastics. His work has been published in over a dozen peer-reviewed journals and conference proceedings, and he has written 1000+ technical blogs on PCB design for a number of companies. He is a member of IEEE Photonics Society, IEEE Electronics Packaging Society, American Physical Society, and Printed Circuit Engineering Association (PCEA), and he currently serves on the INCITS Quantum Computing Technical Advisory Committee.

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