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    Fly-by Topology Routing for DDR3 and DDR4 Memory

    Altium Designer
    |  December 7, 2018

    PCB Panelization

    For years, Harry and Sam had planned to start their own business. After lots of trial and error, they finally received funding from financial supporters who liked their ideas. As plans turned into reality and vision became strategy, Harry and Sam began to focus on a name for their business. None of their initial ideas seemed very good. Since Harry loved flying and Sam had a night job, they decided to look for names that combined the two activities. Finally, Harry’s wife, Berniece, said, “Why don’t you guys call it “Fly-By Night Technologies.” And… so they did! Unfortunately, they didn’t know the meaning of “fly-by night” and wondered why no one wanted to buy their products.

    Fortunately for us, we can rely on fly-by topology. After all, fly-by topology reduces simultaneous switching noise by supporting write leveling, works well with high-frequency applications, and reduces the number and length of stubs. Since fly-by topology offers the best signal integrity for DDR3 and DDR4 memory, we should learn more about how it affects routing.

    General Rules Apply

    Routing should always begin with design rules. Fly-by topology has a daisy chain structure that contains either very short stubs or no stubs whatsoever. Because of that structure, fly-by topology has fewer branches and point-to-point connections. When working with DDR3 and DDR4, routing with fly-by begins with the controller, starts with Chip 0, and routes through Chip n—or the upper data bit. Routing occurs in order by byte lane numbers and data byte lanes route on the same layer. Routing can be improved by swapping data bits within a byte lane.

    If the board design has sufficient space, the address/command/control/differential clocks should route on the same layer. However, it is possible to route on different layers. The Address/Command/Control/Differential Clock routing also starts at the controller and progresses from the lowest data bit chip to the highest data bit chip. This means that there should be no less than 200 mils of space between the memory chips.

    As you begin to place components, it’s important to set aside space for fan-out, the termination resistors, and the termination power supplies. Additionally, your routing plan must avoid routing through via voids on the plane. The vias should spread out and allow for two or more traces to be routed between the vias. Spreading the fanout increases the number of routing channels.

    Routing with strong signal pathing management

    High-speed routing designs within your PCB design software

    Given the complexity of larger numbers of routes, you should use the schematic as the foundation for your design. With the schematic in hand, you can locate key components and nets. With this technique, you can use cross-selection and cross-probing from schematic components and nets to highlight the same item on the PCB.

    High-Speed Circuits Require Different Strategies

    High-speed circuits have greater levels of signal sensitivity and utilize complex constraints to guarantee that an interface works as planned. One approach to achieving greater signal sensitivity and constraints involves bundling the data byte lanes. Following this technique simplifies the routing process. When reviewing your route connections, check for routing channels that have little or no use after a breakout. To ensure that a clean breakout occurs, your connections should occur in sequence.

    Furthermore, your routing plan should avoid crossing routes. To accomplish this, use pin swapping on the memory side to solve route crossing problems. After pin swapping, you can establish a direct or trunk route to complete the connections while reducing the spacing.

    Using Altium Designer® for Fly-by Route Design

    High-speed circuits are complex and require planning for component placement and spacing. With Altium , you can select and use design rules for your PCB; to do so, simply select Design and then Rules from the menus to display the “PCB Rules and Constraints Editor.” Selecting a rule type shows all the defined rules of a certain type as well as the rule priority.

    Altium ’s  3D environment

    Make sure to be able to check your designs in a 3D environment when done

    Good route planning can make the difference between an effective PCB design and a design that lacks performance. Overall, you should build routes that result in a direct path and an interconnect solution for each side of the bus. Altium offers interactive routing features that assist with the design of high-speed, multilayered PCBs. Routing tools include a differential pair router and autorouting for PCB topologies; using the Design menu, you can easily select the Layer Stack Manager to add and route layers.

    To learn more about fly-by topology routing for your DDR3 and DDR4 memory devices, talk to an expert at Altium.


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    About Author

    About Author

    PCB Design Tools for Electronics Design and DFM. Information for EDA Leaders.

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