For those of you who pay attention to Altium’s Youtube channels, you know that signal integrity is a hot topic and it generates a lot of questions. I recently received an interesting question from a viewer that asked about terminating capacitive loads:
I see there are a lot of great videos for impedance matching and designing the width of traces to match any incoming cable impedance, but what about matching capacitive loads?
Current generation MOSFETs and GaN HEMTs are capable of sub 100 ns switching at this point and so I feel like matching to the gate of a power device is going to become a much bigger issue in future…
As I’ll explain below, the idea of a purely capacitive load is something of a fallacy. Yes, capacitors exist, but all capacitors are non-ideal, and it is this deviation from a theoretical capacitance that determines how to impedance match a load that exhibits capacitive behavior. Let’s take a look at this important aspect of interconnect design and see what it really means to terminate a capacitive load.
Very simply, purely capacitive loads do not exist. Even banks of capacitors are not truly “capacitive” loads, at least from a reactive power perspective. In electronics, and specifically in PCBs, a load that appears to be capacitive will only do so in a certain frequency range, and the capacitance may not arise due to intentionally placed capacitors.
Instead, in electronics, when we say a load is capacitive we are most likely referring to a component’s impedance, or specifically its input impedance. A capacitive input impedance generally decreases with increasing frequency and causes current to lead voltage in phase. Some examples include:
In other words, the element is approximated as a capacitor, even if it does not exactly act as such. With this in mind, let’s explore two main cases where capacitive impedance and termination are considered: narrowband analog signals and broadband digital signals.
If you’re only working at a specific frequency, or at a very narrow range of frequencies, then you want to use a standard LC filter circuit. Specifically, a group of two capacitors or an L-filter will normally be used to determine the The key here is this: the real part of the load impedance must be greater than zero. This reflects the fact that, for a real load, it will not be purely capacitive.
To fully impedance match an entire interconnect, you should use the following process:
The different impedances used for a capacitive load are shown below. Typically, the matching network will be an L-match network or a pair of capacitors/inductors in a pi arrangement with the load. The designer can pick high pass or low pass functionality in the matching network and apply circuit analysis to get Zeq.
Step 1 is foundational in circuit analysis so I won’t show an entire explanation here, I’ll probably cover this in another article. You can find a great tutorial at this link (starting on Page 3). In Step 2, the target (equivalent) impedance you calculated in Step 1 becomes the load used in the input impedance calculation in Step 2. Finally, In Step 3, you may need to apply an additional matching network to match the source impedance to the (line + filter) input impedance.
I mentioned above that the source may need to be matched to the input. What I mean is, if the line is slightly longer than the limit for an electrically short line and there is some residual mismatch, the (line + filter) input impedance may be quite different from the transmission line’s characteristic impedance. Therefore, you need to set the source output impedance to match the line’s input impedance at the required frequency. This is done with another matching network (see below). This could be as simple as a series resistor, although in reactive circuits with a transmission line it sometimes makes sense to also use an LC circuit for impedance matching at the required frequency.
You might be thinking: why can I only use inductors and capacitors to match to an arbitrary capacitive load if I need to have a real load impedance? The truth is that the load impedance will have a very small real part. Even for printed components or arbitrary impedances, the load circuit will always have some parasitic resistance somewhere in the circuit. This will arise on the component leads, PCB traces, and any other structure in the PCB layout used to make a connection.
If the transmission line is short, then things are much easier. In this case, you do not need the Input Matching network shown above. With a short line, the source impedance Zs only sees the load, so you can use the source impedance as your impedance target designing the Output Matching circuit block. In RF circuits, this is not what you typically see, there is propagation to another circuit block (cable, transmitter, etc.), so there will be some input impedance deviation to consider.
We don’t always bring this up when discussing high speed logic circuits, but the inputs to CMOS logic circuits have some capacitance that is determined by the transistor and packaging dimensions of the receiver. All transistor-based logic circuits are capacitive, as are the traces that are used to guide the signal to the inputs. The trace and the packaging together have some parasitic capacitance that needs to be charged up in order for the propagating signal to be interpreted as the desired logic state.
The difference between a transmission line and a capacitive load is that a transmission line is really a lumped LC circuit (really an RLC circuit) with complex dielectric constant. Therefore, it’s impedance is approximately real. However, the load capacitance does create real effects; typical load capacitance values can vary from 1 pF to 100 pF for modern digital components, depending on packaging and technology node. The load capacitance is in parallel with a high impedance logic circuit (order of 1 MOhm), so together they act like an RC circuit once they receive the incoming wave. Therefore, we only worry about applying termination as if everything were made of resistors; we only care about frequencies up to the limits where load capacitance takes over.
Clearly, this is a “capacitive” load. In digital circuits, we acknowledge that load capacitance is a bandwidth limiting factor; it only becomes important when you get into the high GHz frequencies, meaning we only care when the roll-off frequency range for this input impedance overlaps with a significant fraction of the digital signal bandwidth. It is not practical to apply broadband termination in these circuits to fully suppress reflections. There will always be some reflection that occurs when the traveling signal reaches the load.
Therefore, the industry has focused on things like equalization and multilevel signaling schemes to recover signals and increase data rates for a given rise time. In any case, the terminating element may be present on the component die unless specialty logic is being used. An example with parallel termination is shown below.
An alternative here is the use of RC termination at the receiver, but this is less common and would require an external pair of components. The idea here is to slow down the rise time, which would normally be limited by the device construction on the die (normally a high impedance input). RC termination is generally not preferred for this purpose as it's better to slow the signal at the driver rather than at the receiver. However, you may not have a choice in some cases, for example when the driver is not located on your PCB and you only have the option of placing an RC termination at the receiver.
The takeaway is this: for digital integrated circuits, we don’t worry about capacitive termination necessarily because we are trying to impedance match over the broadest possible bandwidth rather than at one specific frequency. This puts most of the emphasis on physical channel design to ensure return losses are minimal on short channels and insertion losses are minimal in long channels. If we only cared about matching at one specific frequency, we might lose the majority of the power in the signal and it might be completely lost.
Just to summarize, here are a few important takeaways:
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