What Are Chiplets and How Are They Used in Packaging?

Chiplets are small IC dies with specialized functionality. These are designed to be combined to make up a larger integrated circuit, following the semiconductor industry’s trend of heterogeneous integration. The ability to select from a selection of small, highly specialized chips, and then mix and match these to produce a desired overall functionality, is a major step up from the traditional system-on-chip (SoC) approach to semiconductor packaging. Major vendors have produced computer processors that combine a select number of chiplets, rather than going down the traditional route of monolithic semiconductor manufacturing, where the device is fabricated on a single piece of silicon.

Although the idea of chiplets has existed for decades, chiplet-based packaging is driving new types of components, products, and systems for specialized applications. These components are tailored for specific applications, and more companies are getting into the chip design game with a focus on chiplets as their core processor. Based on the number of research papers, patent applications, and technical articles you’ll find online, it’s clear that chiplet-based components are here to stay.

If you’re a system designer and you’re weighing processor options, you may not realize that chiplets make up the foundation for your system. However, chiplets are the backbone enabling diverse functionality found in modern chips, and the packaging concept is continuing to drive the integration of new features into chip designs. Examples include the integration of FPGA blocks and AI accelerator blocks into the same package as memories, a CPU, and even RF components.

Why Chiplets?

Cost and performance are the two most pressing issues in chip design and manufacturing. Recent years have seen Dennard scaling and Moore's Law slow down, resulting in longer time spans between process technology nodes. Furthermore, transistor integration on a monolithic chip is getting increasingly challenging as there are few options available for device scaling. These challenges have decreased ROI for monolithic semiconductors due to more costly manufacturing processes.

The only way to increase the number of integrated functional units with the same transistor size is to expand the chip area, either in the device plane or vertically. The problem with increasing the chip area is that the bigger chips are more susceptible to manufacturing defects, which limits wafer yield and increases the price of products delivered to customers. Consequently, monolithic chips are becoming increasingly incapable of providing the desired performance in light of the rising computing demands.

Therefore, to support high-compute applications like on-device AI/ML, ultra-fast networking, sensor fusion, and next-gen mobile devices, we have seen an emergence of chiplet-based systems for cost-effective development of high-performance electronics. This has spanned from advanced SoCs to desktop/server processors and GPUs.

Climbing the “Area Wall”

The "area wall" issue is the result of a mismatch between high-performance computing systems' need for large-area chips and the low yield of semiconductor manufacturing. The area wall refers to this challenge in monolithic semiconductor manufacturing, where larger chips are used to increase feature density, yet defect count increases as well. As manufacturing processing capabilities move to more advanced nodes, the process yield decreases, and thus the cost for the end customer increases. Therefore, there is always motivation to de-risk manufacturing for these products by eliminating chances for defects.

A solution to the area wall would reduce the overall cost of an end product by reducing waste during manufacturing. Chiplets essentially diversify the risk profile for a product by spreading it across multiple semiconductor dies. The end result is reduced cost and the ability to greatly diversify functionality to a much greater extent than in a monolithic component.

Reduced Cost

Multiple chiplets are combined with special packaging techniques to make up a larger IC as an alternative to a monolithic structure. Since chiplets are manufactured on a smaller area, usually on circular wafers, the impact of manufacturing defects is reduced and area utilization increases. Consequently, the cost is reduced because the wafer yield is significantly higher when chiplets are used to create a component.

Heterogenous integration is another significant advantage of chiplets, particularly in terms of reducing IC design and production costs. Each chiplet can be manufactured using different process nodes, something which AMD revealed was done with their Ryzen 7 product. Another example from AMD is a recent patent for a chiplet-based GPU; the architecture for this system is shown in the original artwork below:

Multiple materials (e.g., GaN and Si chiplets) can also be combined into the same package with this approach. The use of different process technology nodes reduces the overall risk built into the product; the highest risk is only confined to the chiplet that is being produced at the most advanced process node, rather than across the entire chip.

Design Reuse

Once a chiplet is developed it can be reused, reducing the cost of testing and verification. The cost efficiency of the chip design process is significantly higher through the use of chiplet modules because they can be reused. One scenario of chiplet reuse is to only design and manufacture the core chiplet for an IC, while the remaining chiplets in the package are acquired from another vendor. Using this approach with ready-made chiplets from multiple vendors, or by reusing IP in a new design, greatly reduces the total design and verification costs of the product.

In case any update to the system is required, one chiplet can be swapped for another chiplet inside the packaging. Note that the packaging itself might need to be updated, but this is much less difficult of a design task than redesigning an entire monolithic component. A small portion of the system could also be redesigned without incurring new verification costs that would arise in monolithic semiconductor packages. This method of chiplet-reuse is termed “heterogeneous reuse”.

Another scenario of chiplet reuse is integrating multiple identical chiplets into the same system. This method is ideal for scalable systems and significantly improves their efficiency while reducing cost. This is referred to as the homogenous reuse method and the main advantage is that increasing the number of chiplets in the architecture is all it takes to meet the various performance and power requirements.

Chiplet Packaging Technologies

To make chiplet-based products, you need design skills, dies, connections between the dies, and a production strategy. The performance, price, and maturity of chiplet packing technologies have a substantial impact on the application of chiplets. According to the differences in connection medium and methods, the packaging technologies used for interconnection of chiplets can be classified into three groups:

• Substrate packaging

• Silicon-interposer packaging

• Redistribution-layer (RDL) packaging

• Embedded multi-die interconnect bridge (EMIB)

Substrate-Based Packaging

In substrate-based packaging, the popular choice of substrate is an organic material as these are readily available. Similar to conventional PCBs, wiring connections are made through an etching process that is independent of other processes used in semiconductor manufacturing. This is best known as the earliest incarnation of 2D heterogeneous integration.

Through flip-chip design or stacking, several dies can easily be joined to a substrate with a high density. Moreover, the materials and manufacturing costs associated with it are minimal because this technology does not depend on the chip manufacturing process. The main drawback of using this technology is the low density of I/O pins and the resulting limitation in the bandwidth of the interconnects in these packages.

Silicon Interposer Packaging

This technology spans 2.5D and 3D packaging technologies, where chips are built out laterally on an interposer (2.5D) or stacked vertically (3D). To implement interconnects and communication between dies, the silicon interposer layer is placed between the substrate and the dies. The interposer is like a miniature printed circuit board, essentially providing a substrate for electrical connections between chiplets. The interconnect fabric is built from metallic contacts (called micro bumps) and through-silicon vias (TSV) running internally in the package. These are used to connect the die to the interposer, and the interposer connectors to a package substrate with a BGA land pattern.

These products have a higher I/O density with reduced power consumption and lower transmission delay. This is enabled by the smaller trace length and pitch between micro bumps and TSVs. The only significant drawback of this technology is the increased fabrication costs.

RDL Packaging

Redistribution layer (RDL) packaging technology does not use a substrate, instead involving direct deposition of the dielectric and the metal directly on the top surface of the wafer. This technology is also referred to as ‘fanout’ technology. To carry the wire design, a redistribution layer is constructed such that the I/O ports on each chiplet are shaped around the device. By shortening the length of the circuit, RDL provides greater signal integrity (lower loss and distortion).

Embedded Multi-die Interconnect Bridge

EMIB is a technology that uses thin silicon wafer sections embedded in organic materials as substrates for die-to-die interconnects. The issue of higher costs in advanced products can be tackled by using bridge packaging with diverse chiplets. This hybrid packaging technology is a combination of substrate-based and interposer-based packaging. Thin silicon layers, usually less than 75 microns, are coated onto the substrate and used to form inter-die connections, and these layers are embedded in an organic substrate layer..

The concept follows the same ideas in ELIC used in HDI PCBs, where an every-layer interconnect fabric connects multiple dies to internal layers in an insulating (organic) substrate. The EMIB portion of the package is a silicon bridge that provides high-bandwidth connections between chiplets.

Conclusion

Chiplets are expected to continue revolutionizing applications requiring high-compute components as well as diverse functionality in a single package. These products are currently targeting advanced technologies like 5G, IoT, automotive, edge computing, medical imaging, edge computing, AI, mobile devices, and much more.

Today, major semiconductor manufacturers like Intel, Marvell, and AMD have ventured into chiplet technology, and we can expect more companies to explore this option. As a market develops for chiplet IP, similar to the way a market has developed for many other components, more fabless semiconductor companies may take a custom semiconductor approach rather than building systems with discrete components.

Now that Intel, AMD, and TSMC have agreed on a common standard for chiplet interconnects, will we see a greater proliferation of these designs by other companies? One can hope a market develops for these components as this will encourage more innovation at the packaging level beyond the big semiconductor manufacturers.

As chiplet-based components with advanced packaging come on the market, systems designers can use the advanced search and filtration features in Octopart to find all the advanced components they need for advanced designs. When you use Octopart’s electronics search engine, you’ll have access to up-to-date distributor pricing data, parts inventory, and parts specifications, and it’s all freely accessible in a user-friendly interface. Take a look at our integrated circuits page to find the components you need.

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