Are these capacitors sized properly?
There is quite a bit of information out there about bypass and decoupling capacitors. Both components are vitally important for maintaining power integrity and signal integrity. When you start looking through the information on this topic, you’ll find that the procedure for sizing a decoupling capacitor for a digital IC is quite simple.
Bypassing vs. Decoupling: What’s the Difference?
Although you wouldn’t know it from reading some PCB design guides, bypass and decoupling capacitors do not refer to two different types of capacitors. These two terms refer to the function of the capacitor rather than its design or the materials used in it. Many designers will refer to the two capacitors and their functions interchangeably. In essence, any given capacitor could be used either as a bypass or decoupling capacitor.
The intended idea behind a bypass capacitor is to prevent noise from entering the PCB system from the power supply by “bypassing” it directly to ground. Because a capacitor also acts as a high pass filter to ground, it can be used to pass high frequency noise in the system directly to the ground return. In effect, low level noise present in the output from a DC power supply can never enter the system.
Compare this with another use of a capacitor for power integrity. When placed across the power and ground pins of an IC, a capacitor performs the same function as it would with a power supply, thus it is also sometimes called a bypass capacitor. In fact, it provides the same function as bypassing, i.e., it provides a path to ground with capacitive impedance. However, it performs another function that is quite important, thus this placement makes the capacitor a decoupling capacitor. When one logic IC switches, it can raise the ground potential for itself and other nearby ICs, a phenomenon also known as ground bounce. Connecting a decoupling capacitor to the power and ground pins of an IC “decouples” its potential from that of other ICs on the board.
Although the two terms were originally intended to reference different functions and not different types of capacitors, any designer that wants to ensure power and signal integrity in their board needs to select the right size for their bypass or decoupling capacitor. Some datasheets for different components will stress adding a specific decoupling capacitor (they will often call it a bypass capacitor) between the power and ground pin of a component for signal integrity purposes. Note that this is merelya recommendation, but you would do well to understand how this recommendation was determined.
Equivalent Capacitor Model
In order to choose the right size for your capacitor, you’ll need to examine the basic circuit model for a capacitor. As much as we would like to think that a capacitor behaves exactly as the theory states, this is actually not the case. Therefore, there is an empirical RLC model that is used to explain the behavior of any capacitor.
Equivalent RLC circuit used to model a capacitor
In this model, ESR and ESL are the equivalent series resistance and equivalent series inductance, respectively. The value of C can be taken as the capacitance quoted in a component’s datasheet. Finally, the value of R accounts for the conductance of the dielectric that forms the capacitor. This accounts for transient leakage that occurs in any capacitor after it is charged and removed from its circuit. This value is usually large enough that it can be ignored.
In this model (ignoring R), the value (ESR/(2*ESL)) is the damping constant of the equivalent circuit, assuming the load connected to the ends of the circuit is 0 Ohms. This determines how fast the circuit can respond to a change in the input voltage under full charge/discharge. You should check the data sheets for your capacitor so that you can calculate the damping constant.
If you are decoupling a digital circuit that has a faster switching speed, then you will want to choose a capacitor with an equivalent damping constant that critically damps or slightly overdamps the circuit in order to suppress ringing during discharge. As long as the discharge rate is shorter than the switching time, then the decoupling capacitor will be able to quickly compensate for voltage fluctuations.
Sizing a Decoupling Capacitor for Digital ICs
Note that the above point regarding discharge rate in the equivalent model says nothing about the capacitance. The right way to size your capacitor is to consider the maximum amount of charge that needs to be stored in the capacitor and the voltage fluctuation for which it needs to compensate. Since most loads are capacitive, you can relate the current that reaches the load to the rate at which the voltage of the signal changes from OFF to ON (or vice versa):
Note that you could apply a similar technique to a purely resistive or inductive load.
The best way to show how to use this equation for a capacitive load is with an example. Suppose you have a digital IC with 12 outputs, where each output signal is 5 V with 6 ns rise time. Each output drives a load with 50 pF load capacitance. If you approximate the rise time of the signal as being linear, then the derivative in the above equation can be written as dV = 5 V, and dt = 6 ns. Therefore, the current required per output is:
Current per output from our example IC
If all 12 outputs were to switch from high to low simultaneously, then the total inrush of current from the ground plane is 500 mA. This inrush causes a change in the ground plane potential, which produces a change in the signal potential, and the capacitor should compensate this change in the signal potential. If we suppose the threshold for the ON state is 4.5 V, then the voltage dip that needs to be compensated is 0.5 V in order to prevent bit errors. Furthermore, this must be compensated within 6 ns. Therefore, the minimum decoupling capacitance is:
Minimum capacitance of the example decoupling capacitor
Here, you should use—at least—a 6 nF capacitor to compensate a 0.5 V maximum voltage within 6 ns. Note that some guidelines would recommend using two 3 nF capacitors in parallel in this example as this would reduce ESR by a factor of 2, but this will also reduce ESL by a factor of 2, so the effect on damping is nil. If the capacitor’s response is underdamped, then you may opt for a larger capacitor as this brings the response closer to the critically damped or overdamped cases. However, the use of two capacitors in parallel helps flatten the impedance spectrum of the PDN network near the capacitor’s resonance frequency.
A similar method can be applied to a decoupling capacitor on a power bus, although you would need to consider things like the ripple voltage (or switching speed for a switching power supply), the overall noise spectrum in the output, and your PDN impedance. When multiple ICs appear on the same power bus, a series inductor is sometimes used in addition to a standard decoupling capacitor, forming a decoupling network. These points will be discussed in an upcoming article.
With boards operating at lower levels, higher data rates, and tighter noise requirements, every designer should have the tools they need to select and place bypass and decoupling capacitors for their PCBs. Only Altium Designer gives you schematic design and layout tools you need to create new deigns for any application. Altium Designer’s suite of simulation tools also helps you identify power integrity problems and examine the transient behavior of your power network.
If you’re interested in learning more about Altium Designer, you can contact us or download a free trial and get access to the industry’s best layout, routing, and simulation tools. Talk to an Altium expert today to learn more.
About the AuthorMore Content by Zachariah Peterson