Copper Pour and Via Stitching: Do You Need Them in a PCB Layout?

Zachariah Peterson
|  Created: October 26, 2021
copper pour and via stitching

To pour or not to pour, to stitch or not to stitch… truer words were never spoken in a Shakespearean tragedy! Over many years, some common “rules of thumb” have become very popular and, ultimately, taken a bit out of context. Rules of thumb are not always wrong, but taking PCB design  recommendations out of context helps justify bad design practices, and it can even affect the producibility of your board. As you may have noticed if you’ve read some of the earlier articles I’ve written on these topics, I love challenging some of the conventional wisdom in PCB design, and the two pieces of conventional wisdom I want to look at in this article are copper pour and via stitching.

The use of copper pour and via stitching is sometimes framed as an always-never type of decision, and with a variety of explanations to justify its use or omission. Like many aspects of a physical PCB layout, via stitching and copper pour can be like acid: quite useful if implemented properly, but also dangerous if used indiscriminately.

Copper Pour and Via Stitching Go Together

I first got to thinking about the issue with copper pour and via stitching, or rather via fences, while rewatching Eric Bogatin’s talk for AltiumLive 2020. At one point in his presentation, he discusses the use of copper pour with vias as an example of a common design practice that is, in the view of many, a solution looking for a problem. I have a lot of respect for Eric Bogatin and I think it’s great that he is challenging the conventional wisdom in this area, and I would encourage readers to follow the link above to listen to his remarks. His contention is, in short, that copper pour and via stitching are unnecessary in many designs.

Copper pour around differential pairs
Notice the copper pour around the differential pairs and power/ground islands in this PCB layout.

I’ve listened to several of Eric’s talks and I don't think it's right to make a blanket statement that copper pour should never be used. However, given the audience for the video and time constraints, it makes sense to tell people to omit the copper pour simply because it gets misused so often. I believe he means to say something to the effect of “copper pour is not the magic bullet that will solve all your EMI problems.” I definitely agree with that interpretation. I would not agree with the point at the end of his presentation stating “There is no reason to use copper fill”, although I don’t think he meant this literally; I’ll cite two reasons in this article.

That being said, my company sometimes receives jobs to rework boards that fail EMC, and we have implemented via stitching with copper pour as part of the redesign process. This was done either because it was an intentional design decision or because the client’s engineering team demanded it. These boards usually have multiple problems that contribute to an overall EMC failure, so one can’t conclude that omitting copper pour was the root cause of failure. Conversely, once we’ve reworked some boards with copper pour and carefully selected via stitching (as well as many other design changes), the prototypes have always passed EMC testing. This means that we can't conclusively say that placing copper pour with via stitching was the nail in the coffin for EMI.

Clearly, just including copper pour in a PCB won’t cause your design to automatically fail EMC. So we’re back at the original question: should you use copper pour in your design, or should it be omitted? It all depends...

How Does Copper Pour Affect Crosstalk and EMI?

Two of the supposed benefits are crosstalk reduction and EMI, but this is not universally true, as was shown in Bogatin’s simulation results (see the above video). The main point to take from his results is that crosstalk could already be low, but if a switching signal on one trace excites a resonance in the via structure, that strong noise could couple into the nearby trace.

The graphic below summarizes Bogatin’s results. Those vias along the ground pour are spaced so far apart that resonances could be excited when the aggressor signal switches. There is actually an infinite set of resonances, so a digital signal could theoretically excite any of these resonances as its power spectrum extends out to infinite frequency.

Copper pour and a PCB
The two stitching vias in this copper pour region will have a set of strong resonances that can be excited by a signal on the aggressor trace (left). [Source: Eric Bogatin on Youtube]

So where does via stitching come in? Via stitching or via fences can be used in RF design to suppress resonances at the system’s highest operating frequency. If vias can form a resonant cavity, then an arrangement of stitching vias can be used to suppress plane-pair resonances that would strongly couple throughout the PCB layout. Just like with a via fence, and with Bogatin’s results, if we set the spacing very close then we push the lowest order resonant frequency above the operating frequency in your system. Therefore, you would actually suppress crosstalk. Bogatin’s results showed a nearly 50% crosstalk reduction in this case.

There are three takeaways I see here:

  1. If you are going to use copper pour then you should always ground it, don’t leave it floating. This is a bit of a non-issue as your DRC engine should flag floating conductors as a rules violation anyways.
  2. By making the copper pour wider, you reduce the mutual inductance and the field strength reaching the victim trace. Thin copper pour is basically a guard trace, which will create a structure with high mutual inductance. This is like having a giant resonant cavity that could couple signals between traces.
  3. If you are going to use via fences, set the via spacing small enough that the lowest resonant frequency in the region between the vias is very large. This is one reason we use closely-spaced via fences on waveguides for RF signals; they do provide shielding, but they must be spaced close to be effective so that you don’t excite a resonance that increases crosstalk/EMI.

Did all of this actually solve any severe problem? Not really... The crosstalk was already at about 1%, which is well within noise margins for digital signals, except in probably the most lossy channels. Positioning the vias correctly did reduce this by a significant amount, but crosstalk was already so low to begin with, so why bother? From this perspective on use of copper pour and via stitching, I would agree with Eric that it isn't really useful, and the inexperienced designer could create a new signal integrity problem if these features are not used properly.

To summarize, via fences and via stitching are useful techniques that are sometimes borrowed from RF PCB layout, but only if used properly. If you’re not sure how to use copper pour and stitching vias to target cavity resonances or EMI, then you probably shouldn’t use them.

Copper Pour and Assembly

This is another important point in a design that sometimes gets overlooked. It might seem attractive to solder directly to copper pour in order to make an easy ground connection. However, you should expect a large region of copper pour to have the same effect as a plane layer; it dissipates heat and becomes a DFM/DFA problem when the pour region is large.

When an SMD pad is connected directly to a plane layer through a via, it’s possible that heat would easily dissipate from the pad into the plane. The risks include shifting during reflow, weak/cold joints, or tombstoning in the most extreme cases. This is one use of copper pour that I’ve seen in the past, but that is best to avoid. Instead, use a short trace to connect your solder pads to the nearby copper pour. With large planes, you would place a thermal relief to prevent heat dissipation away from the pad. You could do the same in a large region of copper pour, and it would be more advisable to do this when the copper fill region is larger.

SMD pad copper pour
The bottom SMD pad on R2 is connected directly to a copper pour region.

Routing and Impedance

I’ve pointed out in two other articles how copper pour near traces affects impedance and losses. The important point to remember here is that, for some trace arrangements (coplanar), and for waveguides (grounded coplanar), copper pour and properly placed via fences are required. What you should remember is a critical rule about these arrangements; they only provide high shielding effectiveness when the spacing is much smaller than half a wavelength.

Regarding the effectiveness of vias as shielding, Jon Coonrod writes in a Microwave Journal article:

  • The absence of PTH ground connections in CPW results in less radiation at discontinuities than GCPW, although both circuit types feature superb isolation of adjacent signal channels, resulting in low crosstalk for densely packed circuits.

This just shows that via fences, via stitching, and copper pour around properly designed interconnects can be very useful, but only as long as they are designed and placed properly.

Also, you can bring the copper layer close to the trace in order to set the required impedance for your waveguide. High frequency designs, even operating from 1 to 2 GHz, might use this arrangement. As long as you use an alternative plating (not ENIG), you shouldn’t have such high losses with this interconnect style. You can read more about routing and impedance aspects of copper pour in these articles:

Clearly, there is much more to discuss from the aspect of simulation and measurement, and this debate won’t just end. I think the main point here is to consider the design from multiple aspects and to choose the most important design goal for your system. If you’re not sure why you think you need to add via fences, via stitching, and copper pour, then you probably shouldn’t do it.

The Verdict

Copper pour, via fences, and via stitching are useful tools if used properly, but they could create a new EMI problem if not used properly. Whether or not this new EMI problem is so severe that it interferes with other circuits/components/signals depends on many factors. Contrary to what others might say, there is some evidence that adding copper pour and via stitching can reduce EMI. Take a look at the following references if you’re interested in learning more.

Once thing you'll note in these references: proper use does not involve simply running copper pour throughout the board and placing a single ground connection. These structures are carefully designed to target specific EMI frequencies and problems.

For the rest of us, I think it's important to remember that copper pour with stitching vias will not magically solve every EMI problem. It's one of those design guidelines that was incorrectly applied to situations where it isn't always necessary. My view is that, if you do everything else correctly in the PCB layout, then you most likely don't need copper pour. The corollary to that is, whatever problem you're trying to solve with copper pour with stitching vias was probably caused by something else that is a lot more important (routing, stackup, etc.). If you can solve that problem first, then you might find that you don't need copper pour.

If you do decide to implement copper pour with stitching vias in your next PCB layout, make sure you use the complete set of PCB design, layout, and simulation features in Altium Designer®. The integrated design rules engine and online simulation tools give you everything you need to verify conformance to your design rules as you route your PCB. When you’ve finished your design, and you want to release files to your manufacturer, the Altium 365™ platform makes it easy to collaborate and share your projects.

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About Author

About Author

Zachariah Peterson has an extensive technical background in academia and industry. He currently provides research, design, and marketing services to companies in the electronics industry. Prior to working in the PCB industry, he taught at Portland State University and conducted research on random laser theory, materials, and stability. His background in scientific research spans topics in nanoparticle lasers, electronic and optoelectronic semiconductor devices, environmental sensors, and stochastics. His work has been published in over a dozen peer-reviewed journals and conference proceedings, and he has written 1000+ technical blogs on PCB design for a number of companies. He is a member of IEEE Photonics Society, IEEE Electronics Packaging Society, and the American Physical Society, and he currently serves on the INCITS Quantum Computing Technical Advisory Committee.

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