Decoding Media Independent Interface (MII) in Ethernet Links

Zachariah Peterson
|  January 21, 2021
media independent interface ethernet links

Of all the high speed routing standards, Ethernet comes with an alphabet soup of variant protocols that can mystify the systems designer who might be unfamiliar with Ethernet. The important signal integrity metrics in channel design are rather clear, but other aspects of these protocols don’t seem necessary until you design your first switch.

Most designers (and guides on Ethernet layout/routing) focus on the media independent interface (MII) or reduced media independent interface (RMII) as they’re used for 100 Mbps routing between the MAC and PHY layers in a system. This is fine for most systems running 10/100 Ethernet on a small number of ports, but once you get to gigabit and faster Ethernet, you’ll start to see another group of acronyms, especially once you start looking at PHY transceivers, switches, media converters, controllers, and other components.

The different types of interfaces used in Ethernet systems are very useful if you’re trying to, for instance, miniaturize your BOM in a system with high port count. So how do you approach the different versions of MII for your system? Hopefully, the brief summary of the various protocols below can help you get familiar with system-level design for networking systems that rely on Ethernet.

Media Independent Interface Variants

The standard MII specification is the baseline for other MII-variant protocols running at 100 Mbps and faster. You can find some general guidelines in another Altium article and in one of my recent Signal Integrity Journal articles, but I’ll briefly summarize some basic information on MII and its variant specifications.

MII was originally designed to connect the MAC block of an IC to a PHY transceiver for 100 Mbps (25 MHz clock in 4-bit Rx/Tx data paths). The MII specification is defined by the IEEE 802.3 Ethernet Working group (specifically, under the 802.3u standard) and is intended for connection with a range of different media (e.g., copper or fiber). The goal in this specification is to allow a single networking protocol to interface with a variety of media with a single MAC and external PHY. This central idea is the foundation for all other MII variants.

In addition to the specs I’ve listed here, there are some common qualities to these interfaces:

  • Differential signaling: All signals are differential to ensure common-mode noise rejection.
  • Rx/Tx clocking: Unless you’re doing full-duplex communication in 10G Ethernet (see the table below), there is a separate Rx and Tx clock line.
  • Skew: Unless you’re using one of the serialized variants, your data is running in parallel and should be length matched across a net class. Since we’re dealing with differential pairs, they should be length matched as well.
  • Controlled impedance: These lines need to have controlled impedance, but watch out for different recommendations. The IEEE standard for MII routing specifies 68 Ohm single-ended/100 Ohm differential impedance, while some IC manufacturers will recommend 50 Ohms single-ended + ~30 Ohms series termination.

This is about where the similarities among the MII variants end for designing Ethernet links. The variants differ in signal count, total data rate, clock rate, bus width, and data nibble size. They may also run at different logic levels; make sure to watch for this when selecting components to ensure compatibility. The current set of variants and their specs are shown in the table below:
 

Name

Max. clock/data rate

Bits per clock cycle/signal count

MII

25 MHz/100 Mbps

4 bits/18 signals

Gigabit MII (RMII)

125 MHz/1 Gbps

8 bits/18 signals

Reduced MII (RMII)

50 MHz/100 Mbps

2 bits/9 signals

Reduced gigabit MII (RGMII)

125 MHz/1 Gbps

8 bits/9 signals

Serial gigabit MII (SGMII)

625 MHz/1 Gbps

2 bits (DDR, 8b/10b encoding)/4 signals

High serial gigabit MII (HSGMII)

1562.5 MHz/2.5 Gbps

2 bits (DDR, 8b/10b encoding)/4 signals

Even at 100 Mbps in these specs, Ethernet can be pretty forgiving off of the board as long as the MII routing and PHY output routing are done properly on the board. The clock rates here are pretty low for typical digital components (except HSGMII), but the rise time can be well under 1 ns for the higher data rate protocols. Pay attention to this if you’re testing a prototype; make sure you’ve used a high attenuation ratio probe (10x) and give your scope plenty of bandwidth to examine signal behavior.

Choose the Right Components

If you’re trying to miniaturize your system, take advantage of integration in IC manufacturer product lines. This reduces the amount of MAC-to-PHY routing on the board, reduces component count, and makes routing easier. If you get component count low enough, you might even be able to remove a couple layers from your board. All of this will help you get to a lower BOM cost and simpler overall system architecture, even if you’re working at 10G or with fiber.

For example, some switch ICs with high port count include an integrated PHY interface for gigabit MII variants. For a high port count switch, you may need to use an external PHY transceiver IC to support maybe half of your ports, but that can reduce your routing by 50% or more. If you can then use SGMII to route to an external PHY interface, you’ve reduced signal count significantly compared to simply using GMII to get high data throughput to a large number of ports. This is the type of approach you’ll see in some reference designs, particularly for L2 switches that need high port counts.
 

Media independent interface MII in Ethernet links
There are some switch ICs that integrate a multi-port PHY layer to make this type of 49-port Ethernet switch design easier to manage.

If you want to learn more about gigabit Ethernet, take a look at Mark Harris’ ultra-deep dive into the subject. He does a great job looking more at overall system design (including the PHY output and magnetics design and routing), which should give anyone a good introduction into the topic of GMII/SGMII and faster gigabit Ethernet layout and routing.

If you’re designing IoT products, networking equipment, or embedded systems and you need to route media independent interface connections, use the complete set of PCB design and layout tools in Altium Designer® for your next design. The upgraded Design Rules Editor makes it easy to encode the MII specification requirements as design rules, and you’ll have access to a range of other design tools.

When you’ve finished your design, and you want to share your project, the Altium 365™ platform makes it easy to collaborate with other designers. We have only scratched the surface of what is possible to do with Altium Designer on Altium 365. You can check the product page for a more in-depth feature description or one of the On-Demand Webinars.

About Author

About Author

Zachariah Peterson has an extensive technical background in academia and industry. He currently provides research, design, and marketing services to electronics companies. Prior to working in the PCB industry, he taught at Portland State University. He conducted his Physics M.S. research on chemisorptive gas sensors and his Applied Physics Ph.D. research on random laser theory and stability. His background in scientific research spans topics in nanoparticle lasers, electronic and optoelectronic semiconductor devices, environmental sensing and monitoring systems, and financial analytics. His work has been published in over a dozen peer-reviewed journals and conference proceedings, and he has written hundreds of technical blogs on PCB design for a number of companies. Zachariah currently works with other companies in the electronics industry providing design, research, and marketing services. He is a member of IEEE Photonics Society, IEEE Electronics Packaging Society, and the American Physical Society, and he currently serves on the INCITS Quantum Computing Technical Advisory Committee.

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