Decoupling Capacitor Connections: Traces or Vias?

Decoupling capacitor placement is often reduced to a single layout rule: place the capacitor as close as possible to the IC power pin. That guidance is useful in some package geometries, but it’s not possible in some packages with widely spaced pins or in BGAs with clusters of power/ground pins.

In some layouts, especially large BGAs connected through power and ground planes, the capacitor location is less sensitive than many designers assume, which is something I have discussed in other articles. However, in leaded packages with exposed power and ground pins, a very short direct trace connection with the capacitor placed close to the power/ground pins will still be the preferred connection method. I’ll explain why this is the case in this article.

Package Pin Geometry Determines the Available Connection Strategy

A decoupling capacitor supports a device by supplying transient current across the voltage difference that appears between the device’s power and ground pins. The important factor that determines the appropriate connection method is the path inductance between the capacitor and the pins. The connection method can depend on the type of package involved:

• Common leaded IC packages (SOIC, TSSOP, QFP, etc.)
• Leadless packages (QFNs or specialized no-lead flat-packs)
• BGAs or LGAs with pins buried in the center of the package

Capacitor placement should follow a simple rule:

• The placement of a decoupling capacitor should have minimal path inductance

This ensures current can be delivered sufficiently fast when the connected IC demands power at fast edge rates.

In a leadless package like a QFN or SOIC, the power/ground pins will be accessible around the edges of the package. The power and ground pins may be tightly grouped, but there are some packages that separate the pins around the package perimeter. For a BGA or LGA, power and ground pins are almost always distributed under the package body, and they will be inaccessible from the edge of the package.

Each arrangement points toward a different capacitor connection strategy. I’ve outlined these options in the table below.

Now for the typical placement and routing guidance: the conventional wisdom says that the location of the capacitor matters, but the connection method does not. The reality is that the optimal placement location depends on the connection method, and the conventional wisdom likely assumes that all decoupling capacitors are connected to ICs through trace connections.

Traces, Vias, and Planes in Decoupling Capacitors

First, consider the typical leaded package which might require a decoupling capacitor. The placement of the capacitor should minimize its path inductance; the total inductance along the path will be:

L(total) = ESL + L(traces) + L(vias)

Through-hole vias have fixed inductance based on their geometry; when they appear in the current path they will produce the same inductance regardless of location. However, the total inductance from the traces depends on their length, which is the origin of the “place capacitors close to the pins” rule.

Closely Spaced PWR/GND Pins

Closely-spaced PWR/GND pins provide a natural opportunity to nearly eliminate the trace portion of the path inductance. The example package shown below shows a typical case with 3V3 pins located next to a GND pin, which provides the ability to make very short connections to the pins on the IC package.

In the case where the capacitor is on the opposite side of the IC, the path inductance will still be limited by the vias and the ESL as long as we can still place the capacitor very close to the pins. The moment we use longer traces to connect vias to the pins, or to connect the capacitor to the vias, we add more path inductance.

Separated PWR/GND Pins

Now look at the package below, where the power and ground pins are separate from each other on opposite edges of the package. In this case, you will have two options to connect between the high and low sides of the capacitor: a long trace or a plane. In the example below, a GND plane is used to connect the GND pin on the IC to the GND pin on the capacitor.

Therefore, we will have the total path inductance consisting of the small trace inductance, 1 via, and the plane inductance. Because a plane is used, the total path inductance could be similar to the previous case with closely-placed power and ground pins.

BGA Packages With Internal Power and Ground Pins

Large BGAs commonly place power and ground balls in the interior region of the device footprint. In these devices, directly routing a surface trace from a decoupling capacitor to a specific internal power or ground ball is not possible given the fact that many other traces will require that space. The escape routing and fanout structure push those supply connections into internal planes through vias.

Once the capacitor and the BGA pins both connect into solid power and ground planes, the capacitor location becomes less sensitive than it would be for a trace-connected leaded package. The planes provide a wide, low-inductance current path that usually outperforms any attempt to route long narrow traces toward balls in the center of the package. A capacitor that connects cleanly into those planes can remain electrically useful even when it is not placed immediately adjacent to one specific PWR/GND ball pair.

This is explained in much more detail in the following video:

Placement Guidance for Common IC Packages

For large BGAs, power integrity depends more on PWR/GND plane pairs rather than trace connections to decoupling capacitors. For leaded packages with adjacent power and ground pins, the conventional placement rule becomes valid: the capacitor should usually be brought directly into that pin pair with very short traces. In this geometry, the path inductance will be dominated by the capacitor ESL and the inductance of any vias. A via-to-plane connection can also be used to maintain low path impedance when PWR/GND pins are not placed together.

These common cases lead to two useful layout decisions:

• Use planes when you have a BGA package as the capacitor placement will be much less important
• Use same-side placement on leaded packages in order to eliminate via inductance

As is the case with most layout rules, they come with context, and the context is not often repeated properly (or at all). The two bullet points above provide the context required to understand when the capacitor placement matters and why we might prefer to eliminate vias.

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