How Do Pads and Vias Impact Total Capacitor Parasitic Inductance?

Kella Knack
|  Created: April 8, 2020  |  Updated: October 4, 2020
How Do Pads and Vias Impact Total Capacitor Parasitic Inductance?

As I've discussed in earlier articles, there are many factors at play in determining the impact of inductance on high-frequency power distribution systems. Two topic areas, inductance of the decoupling capacitor and inductance of the power planes, were addressed in earlier articles. This article will focus on the inductance of the capacitor footprint and via inductance from the capacitor footprint back to the PCB power planes. Included are the various types and sizes of footprints for ceramic and tantalum capacitors, and test results showing capacitor parasitic inductance for different capacitors are presented.

    Physical Contributors to Capacitor Parasitic Inductance

    Just to review, equivalent series inductance (ESL) is the capacitor parasitic inductance present in every component due to the fact that its length is longer than zero. It is a major limiting factor in the capacitive response of decoupling/bypass capacitors. Contributors to this inductance include:

    • Physical design contributions from capacitor footprints
    • Capacitor via length to power planes

    The entire path, including the ground return path, determines the inductance of an electrical circuit. This inductance is influenced by the following:

    • Shorter conductors and close spacing between conductors decreases parasitic inductance
    • The inductance of a via back to a plane layer is a function of the distance to the ground return via; inductance increases with via diameter and increases with via length

    In Figure 1 the inductive path from the IC to the decoupling capacitor is highlighted in red.

    bypass Capacitor & IC Path
    Figure 1. Current Path of Bypass Capacitor and IC (red)

    Effective capacitor inductance is a function of the cross sectional area of the loop formed by the capacitor, the capacitor footprint, and the via length to the power planes. The power plane pair between the capacitor and the IC adds to the effective inductance. The IC power via length, spacing between Vdd and ground vias, and the package pin length also contribute to this inductive path, and thus the capacitor parasitic inductance. Note: High performance IC packages have a large number of Vdd and ground vias which form a parallel plane to the power path in order to decrease effective inductance.

    Capacitor Footprints and Via Placement

    The ESL of a capacitor is proportional to the physical size of that capacitor. As a result, large electrolytic or tantalum capacitors have much higher parasitic inductance than do small ceramic capacitors. Furthermore, a 0603 ceramic capacitor has a lower ESL than a larger 1206 capacitor.

    As cited above, two of the contributors to the ESL of a given capacitor are the size and placement of the capacitor footprint. Figure 2 is an example showing capacitor footprints for 1206 and 0603 ceramic capacitors.

    Ceramic Capacitor Footprints
    Figure 2. Typical 1206 and 0603 Ceramic Capacitor Footprints

    As can be seen, the shape of the capacitor along with via placement can change the ESL value of a given capacitor by more than a factor of two. This is because the inductance of a via acts like an inductor in series with the capacitor parasitic inductance. Therefore, the inductances add together. The values in the figure are measured values with capacitors connected to the Vdd/ground plane pair nearest the surface (shortest vias).

    In this figure, when mounted with a typical footprint, the 0603 capacitor has a 40% lower ESL than the 1206 capacitor. The pads in the above figure also have some inductance that appears in series with the capacitor parasitic inductance, therefore the pads also add inductance, even to an SMD capacitor. Larger pads act like inductors with larger cross-sectional area, so they have larger parasitic inductance.

    Figure 3 shows how changing the position of the vias as well as adding more vias can decrease the effective inductance area of the capacitor. This is because the vias are being placed in parallel with each other, and parallel inductors have lower equivalent inductance. This also substantially reduces the ESL value on each lead of the capacitor, giving a simple way to modify the self-resonant frequency created by parasitic inductance in the capacitor leads.

    Power planes and capacitor parasitic inductance in vias
    Figure 3. Two Ways to Place Vias Connecting to Power Planes

    Figure 3 shows there is sufficient space between the pads of a 1206 footprint to place vias between the pads. With four vias being placed between the pads, the ESL is reduced by 53% versus the configuration with two vias. This means that half the required capacitors can yield the same effective high frequency impedance or move the series resonance frequency to a higher value.

    Examples for High Voltage Capacitors

    High voltage applications such as 48V inputs to DC/DC converters require a larger space between surface patterns and prohibit vias from being placed between the pads. This is demonstrated in Figure 4.

    Small capacitor packages with parasitic inductance in vias
    Figure 4. Location of Vias for Small Capacitor Packages

    In this implementation, the vias are placed adjacent to the edge of the pads so that the ESL is substantially reduced from the two-via configuration.

    It should be noted that those capacitors which have a case size of a 0603 capacitor or smaller do not have sufficient space between the pads for the vias, so it’s mandatory that they be placed adjacent to the pad edges. The four-via design in Figure 4 has about 50% of the ESL of the earlier two-via design. Also, in this figure, the choice of 0.05 inch spacing for the 0603 footprint was made so that it could be placed near the edge of a 50-mil pitch BGA while allowing the same routing channels. It’s important to note that if this type of implementation is used, it’s necessary to take care with the design of the solder mask so that the solder doesn’t run into the holes during the reflow process. Alternatively, the vias can be plugged in order to guard against this happening.

    The 0402 footprint via pattern in Figure 4 can fit the pitch of a 1.0 mm pitch BGA. It should be noted, however, that this capacitor size is much more difficult to assemble on a large PCB, so it’s not generally worth the trouble for the small decrease in ESL obtained with the smaller footprint.

    In some instances, the four via footprint configuration is not desirable due to the cost of drilling the additional vias and the difficulty of controlling the tight geometries of the solder mask, as noted above. If a two-via configuration is chosen, such as that shown in Figure 5, it can be very effective as long as the two vias are placed on the sides of the pads rather than on the ends.

    0603 Capacitor parasitic inductance
    Figure 5. Lowest Cost, Lowest Inductance Mounting for 0603 Capacitors

    Figure 5 shows that while the two vias on the side produce a 200 pH larger ESL than the four via example, it’s still substantially less inductance than when the two vias were placed on the ends. In the case of tantalum capacitors, as shown in Figure 6, there are two reasons for having multiple vias on these large capacitor footprints—reducing ESL and ESR.

    6 Via Footprint with low Capacitor parasitic inductance
    Figure 6. Six Via Footprint for a Tantalum Capacitor with a D-size Case

    There are tantalum capacitors available with an ESR as low as 15mΩ. With such a capacitor, a six via pattern can have half the ESL and half the ESR of a two-via footprint.
    Capacitor Via Length to Power Planes

    Table 1 is a listing of several commonly used capacitors. It shows that the ESL of a capacitor is a function of via length to the power plane pair. 

    Capacitor parasitic inductance
    Table 1. Inductance of Capacitors Based on Via Count and Layer Connected to Power Plane Pair

    This ESL is substantially less when a capacitor is connected to the V1/GND pair compared to the V5/GND pair. In Table 1, 13.5 mils is the length of the vias connecting to V1 and 77.5 mils is length of the vias connecting to V5.

    Taking the foregoing one step further, tests were done with identical capacitors with identical footprints mounted side by side. The differentiator was that the capacitors were connected to different PWR/GND plane pairs. These tests were done on multiple stackups (all with thin dielectric between the power and ground planes) with at least two different footprint designs. Equation 1 shows the very close approximation to the measured ESL of a 0603 ceramic capacitor.

    Capacitor parasitic inductance equations
    Equation 1. Equation for Calculating Parasitic Inductance of a Capacitor Mounted on a PCB

    As shown in Table 1, the ESL value can double when the capacitor is connected to a power and ground plane pair on the opposite side of the board. Note: The measured ESL value of a Johnson 0603 capacitor was 120 pH higher than that of the AVX capacitor. The assumption is that this was due to the Johnson having a slightly thicker outer dielectric layer. The increased inductance was observed on several batches of both 10 nF and 100 nF 0603 capacitors.

    Summary

    Capacitor footprints along with vias from the capacitor to the PCB power plane add significant unwanted inductance to a design. Simple design choices, such as the number of vias used to mount an SMD capacitor to its pads and shortening the length of through-hole leads can go a long way to limiting capacitor parasitic inductance.

    Use Altium Designer’s IPC® compliant footprint wizard to make unified PCB library footprints or Talk to an Altium expert today to learn more.

    Reference

    1. Ritchey, Lee W. and Zasio, John J., “Right The First Time, A Practical Handbook on High-Speed PCB and System Design, Volume 1.”

    About Author

    About Author

    Kella Knack is Vice President of Marketing for Speeding Edge, a company engaged in training, consulting and publishing on high speed design topics such as signal integrity analysis, PCB Design ad EMI control. Previously, she served as a marketing consultant for a broad spectrum of high-tech companies ranging from start-ups to multibillion dollar corporations. She also served as editor for various electronic trade publications covering the PCB, networking and EDA market sectors.

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