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New Multilayer Architecture: Power Mesh

Happy Holden
|  Created: July 23, 2019  |  Updated: November 29, 2020

It’s funny how we accept the status quo as the only reality because it’s the only existence we’ve been subject to. In printed circuit design, the multilayer architecture is one such status quo. But it is not the only architecture that will work for high-speed designs. At Hewlett-Packard, we experimented with and implemented a higher performance architecture based on RF Design characteristics. It was not by accident, as our PCB design organization also shared resources with our IC design organization. One day, I was reviewing a paper written by Dr. Leonard Shaper of HiDEC (part of Univ. of Arkansas) on Interconnected Mesh Power System (IMPS) [1,2,3]. This was a high-density architecture created for design of 2-layer thin-film MCM substrates, where each layer contained power ground and signal ground and there were no planes. In those days, the only way to get down to 10-micron geometries was to employ thin sputtered metals and semi-conductor photoresist lithography. I thought at the time, “Why don’t we try this with 5-mil (0.125mm) geometries on FR4 to see if it will work?” Figure 1 shows the three architectures and design rules.

We tried the architecture on a current 12-layer disk drive board and were able to complete the design with only 4-layers (we didn’t move any parts). 

WOW!—that was easier than we thought! Our IC designer friends, looking over our shoulders, commented, “Good going—this is how we design integrated circuits”. Our RF customers also commented, “Nothing new—this is an offset co-planar stripline structure—been using it for 30 years!” So, we didn’t invent something new (as we learned when we tried to patent it) but it sure worked better and had higher densities than the conventional multilayer architecture while also having a lower inductance PDN. We called it “POWER MESH”, and kept it as ‘OUR’ secret!

FIGURE 1 a. The conventional multilayer architecture; b. the IMPS architecture of only 2-metal layers; c. The HP Power Mesh architecture of 4-layers. 

Impedance Control

Figure 2a shows the single power plane. The next step is a split power plane (fig2b). Power Mesh uses RF coplanar structures to apply as many as 12 separate power rails to layers 3 and 4, but orthogonal (Fig2c). The same PDNs are connected to layers 2-3 with buried vias (Fig2d). Transmission lines for routing, either single-ended or differential, was a major concern with this architecture. As seen in Figure 2 (fig2e), all traces are coplanar and referenced to the close ground plane, but also coupled to power. Fig2f shows the design rules for 50 ohm and 100 ohm differentials.

Figure 2. The offset coplanar stripline structure has many advantages for high-speed signals-low crosstalk-low PDN impedances; .a.  

Layout and Design

PCB layout is unconventional but straight-forward. The difference is that first you create a power grid, on which you place the power pins for devices on this grid, after calculating the width of the power traces. To ensure there is no voltage drop, you use a mesh to connect all the devices on layer 1 and 4 by blind-vias. The PDN mesh must be completed in X & Y; routed back to your power sources using buried vias. This mesh acts like a plane in that power has various routes to the devices.

Protect all the power connections and mesh and start the routing of signals in the X and Y layers. It is ‘OK’ to ‘push’ power mesh if the power-pin connection is maintained. Once routing is complete, all the power traces are expanded to fill all available spaces (as polygons) to maximize distributed capacitance for each PDN. Figure 3 is a summary of the design steps.

Figure 3. The design process for Power Mesh has familiar activities but re-arranged in terms that the PM structure is done first.


One of the many examples we used to train designers and engineers is seen in Figure 4. This high-speed multilayer was originally designed with 12 layers. The power mesh version needed only 4 layers and was completed in just 2 days, as we did not move any parts. In later reviews we realized that if we moved 48% of the parts to the far-side, the board could be ½ the size - or we could merge a second board on the backside.

Functional testing indicated lower crosstalk and lower PDN impedance, along with the cost reductions of 8-layers to 4-layers. Further cost reductions could be expected if we placed many of the components on the far-side. 

There are no published papers on this topic as we kept it a secret for 30 years!! But if you ‘Google’ “power mesh”, you will see articles on IC design. GO FOR IT!

Figure 4: An example of a conventional 12-layer TH HS multilayer redesigned to 4-layer Power Mesh. (later analysis indicated the board could be ½ the size or a second TH integrated into this PM version). A. Layer-2 Y routing of signal & PWR; b. Layer-3 routing of X routing of signal and PWR; c. Two of the conventional 12-layer inner layers; d. Layer-1 surface ground-pour and SMT lands including side-view. 



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  1. L.W. Schaper, S. Ang, D.A. Arnn, J.P.Parkerson, “A Low-Cost Multichip Module Using Flex Substrate and Ball Grid Array,” Proceeding of the ICE on Multichip Modules, Denver, CO, April 1996, pp. 28-32.

  2. Schaper, L & Grover, M, “Comparison of the Interconnected Mesh Power System (IMPS) and Buried Stripline Interconnect Topologies in Microprocessor Packaging”, 5th IEEE Workshop on Signal Propagation on Interconnects, June 2000, San Francisco, CA

  3. Schaper, L; Parkerson, J; Brown, W; & Ang, S; “Modeling and Electrical Analysis of Seamless High Off-Chip Connectivity (SHOCC) Interconnects”, IEEE Transactions on Advanced Packaging, Vol.22, NO.3, August 1999

About Author

About Author

Happy Holden is retired from GENTEX Corporation (one of the U.S.'s largest automotive electronics OEM. He was the Chief Technical Officer for the world’s biggest PCB Fabricator-HonHai Precision Industries (Foxconn) in China. Prior to Foxconn, Mr. Holden was the Senior PCB Technologist for Mentor Graphics; he was the Advanced Technology Manager at NanYa/Westwood Associates and Merix Corporations. He retired from Hewlett-Packard after over 28 years. His prior assignments had been as director of PCB R&D and Manufacturing Engineering Manager. While at HP, he managed PCB design, PCB partnerships, and automation software in Taiwan and Hong Kong. Happy has been involved in advanced PCB technologies for over 47 years. He has published chapters on HDI technology in 4 books, as well as his own book, the HDI Handbook, available as a free e-Book at and de recently completed the 7th Edition of McGraw-Hill's PC Handbook with Clyde Coombs.

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