PCBs With Double-Sided BGA Placement

Some designs get so dense that there is no choice but to place BGA packages on both sides of the PCB. Sometimes, these packages overlap, creating a challenge for BGA fanout routing and via design. This happens, stackup planning for either multiple laminations or blind and buried microvias will be a requirement to handle overlapping BGAs.

I'll break down strategies for double-sided BGA placement and overlapping BGA placement which will help ensure your designs can be successfully routed. Designing the stackup the correct way ensures both successful routing and ensures that the vias in your BGA fanout can be fabricated successfully. What we will find in this article is that double-sided BGA placement tends to drive high layer counts, as this will be the only way to fully route the PCB layout.

Double-Sided and Overlapping BGA Layouts

Mechanical constraints like board size and connector placements are the most common reasons for overlapping excited placement of BGAs in a PCB layout. Similarly, you could also have QFNs or QFPs overlapping with a BGA on the other side of the board, and the strategies for routing I'll discuss below will still be the same.

Double-Sided BGA Via Arrangements

First, let's consider what happens when we have double-sided placement of BGAs. Typically, we will have some signals that route between these two components. The BGA pitch could be different and thus they might require different via types for fanout routing (for example, through-holes versus blind/buried vias). The distribution of ground and power pins could also be different; on larger processors the power pins are often clustered in the center of the component, while a BGA-type connector or an ASIC in a BGA package could have power and ground pins spread out. These factors will influence how signals are routed between the two components.

Double-sided BGA placement with through-hole vias for routing.

In the double-sided BGA placement, the two BGAs are offset from each other. Depending on the pitch of each BGA, the fanout routing could involve a mix of through-hole vias, mechanically drilled blind or buried vias, or microvias on a standard HDI stackup.

I have outlined some typical routing cases of these BGA arrangements in the table below.

In any of the above arrangements, the smallest pitch BGA will determine required stackup fabrication and the number of HDI build-up layers, while the largest BGA will determine the number of layers. This means that, for example, you could have one BGA fanned out with stacked or staggered blind/buried vias, and another BGA fanned out with through-hole vias.

I have found that the smaller BGA often has the finer pitch and will be the most likely package to need microvias. A typical PCB stackup for these designs might look like the via arrangement shown below.

This is a standard HDI build with multiple blind buried microvia layers. If the microvias are not needed, they can be eliminated and only mechanical drills would be used. One possibility to aid routing through the BGA region is to use through-holes and a buried via such as the stackup shown below.

Example routing with a buried via between two fanouts with through-hole vias.

I like this via design because the buried via could be used beneath the outer edge of the larger BGA to assist with layer transitions if needed. However, it is not required. I'll look at this more in the next section on routing.

Note that if a buried via is used, it will require heavier copper on the outer layer because the outer layer will get plated when the buried via sub-lamination is fabricated. This could then force you to use a larger pad oversize in order to comply with IPC annular ring requirements depending on if you are building a Class 2 or Class 3 product. The same applies to sub-laminations built with mechanically drilled blind vias. Read more in this linked article.

Double-Sided BGA Routing

Once the via transitions are set up in the PCB layout, we can route signals between the transitions. Through-hole vias are easy to work with, simply route traces across wherever there is an open layer. It can be difficult to do this when one of the traces has to route between an outer row on one BGA and an inner row on the other BGA. The challenge comes from choosing which layer to use. I tend to prefer using the outer row of the larger BGA as the starting point for routing between the two BGAs.

While it would be nice to route straight across between the two BGAs, I have found that this is almost always impossible to do for all pins. This is due to crossover at differences in row location for the pins on the different BGAs. Therefore, you should allow some space between the two BGAs for through-hole vias or buried vias to make the required layer transitions.

Example with a 2-sub-lamination PCB stackup and through-hole routing between the two BGAs. Note that the entire stackup could also be built with through-holes as long as plating limitations allow (see the DFM section below).

Through-holes are typically the best choice because you might have to reach the surface layer of the destination BGA with one of your routes. However, a simple stackup with a single buried via and through-hole vias also enables this kind of routing.

Overlapping BGA Routing

The other case where two BGAs take up space on both sides of the board is when the two BGAs directly overlap. I have dealt with this in two contexts:

• Where two large BGAs of similar pitch overlap each other
• Where a large BGA overlaps with multiple smaller BGAs

In both cases, the required stackup will be the same and it will involve blind vias.

Just as was the case with the double-sided BGAs, the largest BGA will drive the required number of signal layers, while the smallest pitch BGA will determine the required fabrication technology. For a larger pitch BGA, such as 0.8 mm or 1 mm, I would advocate use of a sub-lamination build with mechanically drilled blind vias. An example with two sub-laminations is shown below.

For this type of situation, you might as well use blind vias spanning all the way to the central dielectric, and design the stackup for a prepreg to bond the two sub-laminations together. There will not be any value in placing blind vias to a higher layer as you miss out on available routing for power and signals.

If you want via connections through the entire stackup or you have fine pitch BGAs, use stacked blind/buried microvias fabricated with laser drilling (including via-in-pad). With an internal core buried via, this will allow connections between the top and bottom side BGAs.

This routing leaves room for through-holes off to the sides of the overlapping BGAs.

The challenge with this approach, as shown in the image above, is you need to allow additional redistribution routing layers in order to prevent crossover between the two BGAs. You will never have the pins line up perfectly for direct vertical routing between the two BGAs.

Another option is to use a region off to the side from the overlapping BGAs where through-holes can be used to complete the vertical routing. When I work on these types of PCB layouts, I will typically take this approach with mechanically drilled blind vias in the BGA fanout.

PCB Stackup and DFM

Stackups for these designs can get much more complex, depending on the pin pitch and pin count for the various BGAs. It is possible to mix via technologies to build the stackups for these designs. For example, you could have:

• Mixed sub-lamination and sequential lamination builds with both mechanically drilled blind vias and microvias
• Hybrid HDI stackups, where microvias are used on only one side of the PCB
• Large diameter laser drilled microvias for fanning out larger pitch BGAs
• Standard HDI stackups with multiple sub-laminations in the buried core via region

Any of these stackups could technically work to enable routing between overlapping BGAs. However, there are some important points to consider when using either sub-lamination builds or sequential lamination with laser drilled microvias.

Sub-Lamination Builds

When sub-laminations are used, the number of sub-laminations should be minimized due to the small clearances in the BGA region. Ideally, only two sub-lamination sections should be used and bonded together in the core region.

The reason the number of sub-laminations should be minimized has to do with the buildup of copper weight during each sub-lamination build. As I detailed in another article, each sub-lamination that is used with blind vias as part of fanout routing will plate additional copper onto the surface layer. The required pad oversize on the subsequent sub-laminations will get larger and larger in order to comply with IPC annular ring standards. Eventually you risk violating your clearance limits.

I think the most important point to implement when using sub-lamination builds is to ensure the via spans are symmetric, i.e., span the same number of layers on each side of the PCB stackup. Using symmetric blind and buried vias ensures that the resulting plating in each sub-lamination is symmetric throughout the PCB stackup. This is needed to prevent warpage, and preventing warpage is extremely important for ensuring the planarity in the region where the BGA will be soldered. If this region of the board is cleaner due to warpage, then the PCB will need to be scrapped.

Sequential Lamination with Microvias

Whether the BGAs are overlapping or offset on both sides of the PCB, the higher pin count BGA will drive the layer count and the number of buildup layers. However, not all designs can have a high number of buildup layers, either for stacked or staggered vias. There will be some limit based on fabricators' capabilities or your own company's quality standards. When these build-up layer count limits are reached, the design will need to switch from sequential lamination back to a sub-lamination build.

As is always the case with stackups involving blind/buried vias, check the stackup against fabricator capabilities. If this step is done incorrectly, it can quickly invalidate your entire routing between the BGAs. In some instances, it will prevent the fabricator from guaranteeing reliability or force a deviation from Class 2/Class 3.

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