Creative Design with Buried Vias in Your Next HDI PCB

| Created: February 11, 2019 | Updated: April 18, 2025

<p dir="ltr">Blind and buried vias can be very useful tools in a PCB designer's toolbox. If they are not used correctly, or if they are used in an attempt to save an unsolvable layout, they become something of a crutch that just increases cost when it is not necessary. But when used correctly, both blind and buried vias offer some creative design options in many application areas.</p>

<p>Another type of design that eliminates HDI buildup layers but still gives some routing advantages is to make use of buried vias. Contrary to the typical perception of blind and buried vias, buried vias are not only needed when you need an HDI design. While using sequential lamination to build a stackup with buried vias does increase cost, it enables certain types of designs that could be difficult with standard through-hole builds.</p>

<p>In this article, I'll present some creative uses of buried vias in certain types of stackups and application areas. I think when these options are compared with designs involving through-hole plus blind vias, or with designs involving back drilling, the advantages of using buried vias in certain designs will be quite clear.</p>

<h2><a id="good-and-bad-ways-to-use-buried-vias">Good and Bad Ways to Use Buried Vias</a></h2>

<p>The most common use of a buried via is as a core via, such as you would use in an HDI design. In the <a href="https://resources.altium.com/p/2n2-pcb-stackup-design-hdi-boards">stand… HDI stackup designs</a>, the core via is buried in the thick central core region of the PCB stackup, and the buildup film layers are laminated above and below. Variations of this involving mechanically drilled blind and buried vias with large diameters are also possible without using thin buildup layers.</p>

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<p>The standard usage of a buried core via is in HDI PCB design, where the outer buildup layers are sequentially laminated around the core with blind vias.</p>

<p>This all looks pretty simple, right? So what's the big deal with a PCB stackup that only uses a through-hole via and some buried? Here are some designs I have worked on in the past.</p>

<h3><a id="confined-rf-circuits-in-internal-layers">Confined RF Circuits in Internal Layers</a></h3>

<p>Buried vias can be designed to be stubless, which makes them very useful in RF designs involving layer transitions. Although it is conventional wisdom to only keep RF circuits on a single layer as microstrips, there are many examples from real designs where this does not happen. Furthermore, these designs may operate at 10 GHz or higher, and this means stubs on vias could create insertion losses that could fall within an RF system's operating bandwidth.</p>

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<p>By using a buried via, the design can keep breadth routing and <a href="https://resources.altium.com/p/what-rf-circuit-design">RF printed circuits</a> in an internal layer and still provide a connection to components on the top and bottom layer with through holes. An example cross-sectional view of a stackup with this configuration is shown below.</p>

<p>In this example, we would need to back drill two vias on either side of the PCB stackup. In this particular type of design, it may be preferable to backdrill the vias rather than add laminations to the stackup with blind vias, particularly from a cost perspective. We then have the benefit of using buried vias to protect the RF circuits because the buried vias will not consume space for components on the top and bottom layers, allowing the component placement to be quite dense if required.</p>

<h3><a id="cap-core-pcb-stackups">Cap-Core PCB Stackups</a></h3>

<p>There is one type of stackup that can make use of buried vias for routing in internal signal layers without stubs. This stackup is sometimes called a reverse stackup or a cap-core stackup. In this design, we take the traditional approach with outer layer signal routing and invert it so that signals are on an internal layer, much like the <a href="https://resources.altium.com/p/two-alternative-4-layer-pcb-stackups-50-… four-layer PCB stackup</a>:</p>

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<p>With a buried via on the inner layer and ground on the outer layers, the buried vias are primarily used for signal routing only between the inner layers. Through-hole vias would then be used to route signals into a component or to stitch the top and bottom ground layers together.</p>

<p>Building this PCB stackup design requires laminating two layers around the central dielectric with the buried via transitions. Multiple laminations bring higher <a href="https://resources.altium.com/p/how-create-pcb-manufacturing-cost-estima… cost</a>, but the trade-off is much greater freedom of routing between components. By pushing all routing into the internal signal layers with the buried vias for layer-to-layer routing, components could also be placed with much higher density on the surface layers. I like this routing for packaged module designs which require high-density placement of small components.</p>

<h3><a id="eliminating-crossing-blind-vias">Eliminating Crossing Blind Vias</a></h3>

<p>When a designer starts hitting density limitations and needs to avoid placing vias completely through the stackup, they usually start using blind vias first. There is nothing wrong with this approach because the blind vias still need to reach a surface layer in order to make connections to components.</p>

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<p>However, when blind vias start crossing each other in the PCB stackup, it may be better to use a buried via and through-hole vias instead. Blind vias crossing each other creates additional drilling steps during sequential lamination. Because the drills need to be applied across each lamination, there is risk of <a href="https://resources.altium.com/p/how-antipads-affect-signal-integrity-you…; between vias at each lamination. The image below shows how we can trace out lamination interfaces when blind vias are crossing each other in the PCB stackup.</p>

<p>By using a buried via between the two blind via endpoints, two drilling steps are eliminated, one from each of the outer laminations. The outer laminations will also be immune to misregistration between laminations, whereas the crossing blind vias will not. This makes the buried via design preferable to the crossing blind via design from a reliability perspective.</p>

<h2 dir="ltr"><a id="buried-vias-in-your-hdi-pcb">Buried Vias in Your HDI PCB</a></h2>

<p dir="ltr">Using buried vias can also help you reduce the number of layers required to route all of your traces and/or reduce the overall size of your board. Since these vias only run between inner layers, you’ll have more room to route traces on the surface layers. This is useful when fanning out a BGA. If you're using through-hole vias and your escape routing is taking up too much space, you can reach the inner layers with blind and buried vias and widen the breakout channels.</p>

<p dir="ltr">Blind and buried vias also have a cost trade-off compared to through-hole vias. Blind and buried vias incur higher manufacturing costs per via as the board will require additional machining steps. However, they allow denser routing on the surface layers and can be used to reduce the layer count. This might offset the overall cost of the additional machining steps, depending on how creative you can get with your routing.</p>

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About Author

Zachariah Peterson has an extensive technical background in academia and industry. He currently provides research, design, and marketing services to companies in the electronics industry. Prior to working in the PCB industry, he taught at Portland State University and conducted research on random laser theory, materials, and stability. His background in scientific research spans topics in nanoparticle lasers, electronic and optoelectronic semiconductor devices, environmental sensors, and stochastics. His work has been published in over a dozen peer-reviewed journals and conference proceedings, and he has written 2500+ technical articles on PCB design for a number of companies. He is a member of IEEE Photonics Society, IEEE Electronics Packaging Society, American Physical Society, and the Printed Circuit Engineering Association (PCEA). He previously served as a voting member on the INCITS Quantum Computing Technical Advisory Committee working on technical standards for quantum electronics, and he currently serves on the IEEE P3186 Working Group focused on Port Interface Representing Photonic Signals Using SPICE-class Circuit Simulators.