The Right Way to Use Power Planes in a 4-Layer PCB Stackup

Many products are manufactured on four-layer PCBs, and these are something of an entry-level stackup for many designs. From a signal integrity and EMI/EMC standpoint, the easiest four-layer stack to use is the Sig/GND/GND/Sig stackup, as it enables high-speed digital routing with controlled impedances on both sides of the board, but without a requirement for coplanar ground on the surface layers.

Although this is the best stackup from a signal integrity and EMI perspective, I constantly see new designers use a SIG/GND/PWR/SIG stackup when they do not need it. The most common approach is to use the PWR layer on L3 as if it were a solid ground plane while taking advantage of the convenience of routing with a plane layer. While having a dedicated power layer does make routing more convenient, this might come at the expense of signal integrity.

Therefore, in this article, I want to outline some strategies and examples which show how to use this stackup correctly, as well as when it should be used in a design.

The Wrong Way and Right Way to Use SIG/GND/PWR/SIG

Before getting into the design guidelines for this type of stackup, I think it's important to look at some of the wrong ways to use this stackup. Here are some of the interesting ways I've seen this stackup used:

• Splitting the power plane up into many rails, then routing fast single-ended digital signals over the gaps
• Using the PWR layer as a signal layer by routing traces in it
• Omitting stitching vias for signal via return paths
• Using copper pour on the surface above the power plane but omitting it on the other surface

These are some of the basic factors that impact EMI and signal integrity. In some designs that use the SIG/GND/PWR/SIG stackup, the SI problems can be measured but do not seriously impact functionality. However, when a hobby SIG/GND/PWR/SIG design is put through free certification, one may find that it fails EMI testing. Proper use of the stackup can help prevent simple EMI that derail a production project.

Route Single-Ended Signals Over Solid Power Sections

This is one of the simplest ways to prevent EMI from single-ended high-speed digital signals without using silly things like stitching capacitors. In digital designs based on the SIG/GND/PWR/SIG stackup, signals typically originate on the top layer above the ground plane because that is where all the components are placed. For the fast digital interfaces, such as SPI/QSPI, PPI, GPIOs, or memory protocols, routing onto the back layer presents potential SI & EMI problems when the power layer has split regions.

Although we would prefer to avoid routing any of the fast digital signals on the back layer, sometimes it is unavoidable. Confine the routing for these interfaces over a solid region of the power plane with no splits. An example from my recent NFC Reader project is shown below.

Prefer Slower Single-Ended Signals Routing Over Power Plane Splits

If you must route over splits due to the required spans of the power rails, it is better to plan your routing such that slower signals or DC control signals are routed over power rail splits. Signals with slower edge rate will exhibit less radiated emissions and not need to have ground as close to the trace compared to faster edge rate signals. This is a lower-risk option that still allows the designer to route on the back side if needed, but it requires some planning before starting the routing process.

Faster edge rate signals should get priority on the top PCB layer, while slower signals can take priority to route over splits in the power layer. For example, there are some interfaces that will not have problems routing over plane splits:

• UART
• I2C or I2S
• GPIOs driving series resistances

Too Many Splits? Consider GND Pour and Via Stitching

Some four-layer boards with a power layer primarily use the power layer for a large number of rails at different voltages. I have certainly used four-layer stackup designs for this purpose, particularly in power electronics where all the components can't fit on one side of the board.

In this case, you might be forced to route over a large number of splits between the power rails above the power layer just to get signals between components. In this instance, you can do the following to ensure you have a clear return path on the back layer and the top layer for any signals transiting the entire stackup:

• Place grounded copper pour on the bottom layer
• Use the via stitching tool to connect internal and external grounds
• Place pour on the top signal layer above the ground plane to balance the copper
• Place a stitching via close to any signal vias transiting the stackup

The stitching vias near this SPI routing ensure a clear return path is maintained near the signal vias.

This is not a perfect solution and it typically occurs when cost forces you into a four-layer board instead of a six-layer board. However, I have implemented it to correct a radiated EMI problem where certain signals were radiating at the clock frequency and its harmonics. This particular fix allowed the design to stay on four layers.

As I have noted in other articles, copper pour should not be used to fill in empty space on a design indiscriminately. Use the copper pour when you can identify its specific function and ensure it provides sufficient coverage between signals. And if you do find you need to use copper pour, make sure the distribution of pour is symmetric throughout the stackup.

Consider an Alternative: SIG/GND/SIG/PWR

There is an alternative approach that could be used in these four-layer boards demanding a power layer: the SIG/GND/SIG/PWR stackup. This stackup forms stripline routing with one of the signal layers and keeps those signals near a ground plane. This overcomes some of the challenges that arise when using an external signal layer above a split power layer. I think this stackup works best when the power layer is uniform and has no splits. In addition, as I have shown in an Altium Academy video about routing over power plane splits, the effects on impedance do not become noticeable until the GHz range, particularly with stripline routing.

Using the internal routing in this way gives some of the other benefits seen with striplines:

• Very low FEXT between striplines
• Narrower 50 Ohm traces, which allows for denser routing
• Natural shielding from external EMI sources due to the plane layers

Such a stackup would look like the build shown below. A typical layer thickness arrangement follows the typical 4-layer stackup 

On the outer layer, we could also have split rails operating at different voltages, and possibly carrying high DC power. It is best if the power rail outputs are routed onto the back layer as these will be filtered by output capacitors and would be expected to have low ripple/high stability. What you should not do is place any switching node on the back layer above the stripline routing as the switching node will inject noise (as crosstalk) into the striplines.

Another factor is rail capacitance from the nearby ground plane. Because the rails are placed on the back layer far from the ground, there will be very little capacitance to the ground plane on L2 for these rails. This only becomes a power integrity problem when the rails need to power a large number of fast I/Os at low logic level (e.g., 1.8 V or 1.2 V) because there will be very little plane capacitance.

To help overcome this and to ensure balanced copper in the stackup, ground pour should be used to fill in the empty space on L3. You will also need to fill in the empty space on L1 with copper pour to balance copper across the stackup and help prevent warpage.

One interesting option with ground pour on the outer layer and the stripline layer is shown below, where the outer layers are thick cores and the inner layer is thin prepreg. This provides greater coupling of the stripline layer to the GND plane on L2. There will still be some weak capacitance for the power rails to the grounded copper pour on L3. As this does not match any standard stackups which I have seen from fabricators, it will require review and approval before being accepted for fabrication.

Another Option For Power Systems: SIG/GND/(PWR + SIG)/GND

One option I have discussed in an article and video looks at using the power layer on L3 along with signal. You can then use GND on the outer layer to form stripline routing with the signals on L3. These designs follow similar guidelines as the SIG/GND/SIG/PWR stackup:

• Fill the empty space on L1 with grounded copper pour
• Do not put any switching nodes on L3

This PCB stackup works well when the routing on L3 is not too dense and the power rails do not need to be so large that they eliminate space for routing. The outer GND layer then provides shielding for the signals on L3, so the central dielectric layer does not need to be a thin prepreg.

To learn more, watch the following video on this topic or read the design article.

Whether you need to build reliable power electronics or advanced digital systems, use Altium’s complete set of PCB design features and world-class CAD tools. Altium provides the world’s premier electronic product development platform, complete with the industry’s best PCB design tools and cross-disciplinary collaboration features for advanced design teams. Contact an expert at Altium today!