Substrate-Like PCBs Push the Limits of HDI
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Real electronic products have been slowly getting smarter, both from implementation of an embedded application and connections back to a cloud platform or application. Embedded development teams have to work together to create these new generations of products. One area where the PCB layout engineer, embedded developer, and even the MCAD engineer can get delayed in finishing a project is in I/O selection. This happens whenever you have connectors, peripherals, and a host processor.
This particular class of PCBs actually has some compelling market growth that EDA companies and manufacturers should not ignore. The market for substrate-like PCBs is expected to grow at approximately 15% CAGR and reach $6 billion by 2031 as more devices push past the HDI regime. Will your next device need to have high enough densities to be considered a substrate-like PCB? Keep reading to see if you can make use of this technology.
Substrate-like PCBs occupy a middle ground between an HDI PCB and an IC substrate. They could best be categorized as ultra-HDI PCBs as was described recently by Tara Dunn. The technology is not new, and one of the major drivers has been smaller mobile devices or wearables, which need to pack many features into small spaces. This is of course the standard trend in HDI design, but IC substrates push the feature sizes and component densities to extreme levels.
Because a substrate-like PCB sits somewhere between HDI PCBs and IC substrates, I think it is worth comparing these types of components to see what capabilities are required for their fabrication. The image below shows this information as a spectrum, where we cross into the substrate-like PCB domain as linewidths get smaller. The feature sizes and layer counts listed below show how we can broadly categorize different types of ultra-HDI PCBs.
Eventually, as linewidths decrease, these products start to look more like IC substrates that provide interconnections between semiconductor dies (i.e., chiplets) inside a component package.
While the concept of these designs might be new to some designers, these components are not actually new. The substrate industry was dealing with the same challenges many years ago, they were just dealing with direct mounting of semiconductor dies onto a substrate rather than a mix of traditionally packaged components. Substrate-like PCBs essentially target any application using very fine chip-scale packaged ICs that must coexist with traditional ICs on the same substrate. You could also integrate chip-on-board into these packages.
One of the major users of substrate-like PCBs is smartphones, and the products available to consumers today are using substrate-like PCBs. The first instance of smartphones using substrate-like PCBs began in 2017 with the iPhone 8/X, which were fabricated with an mSAP process. Samsung also used the technology in their newer Galaxy line of smartphones.
Given the finite enclosure size, and the demand for more features with a bigger battery, the push is of course to decrease feature sizes on the chips and the PCB. The next generation of substrate-like PCBs is stacked assemblies, where very thin devices are packaged on top of each other with vertical interconnects.
If you look at the above spectrum, it would appear that all substrate-like PCBs and IC substrates must have lower layer counts than a traditional HDI PCB. This might seem contradictory at first, especially if you compare standard HDI PCBs with lower density PCBs built using the standard etching process. What happens when crossing the HDI-to-substrate-like PCB threshold?
The first reason is the materials being used in these designs. Materials used in these boards can be much thinner, both for rigid and modified polyimide substrate-like PCBs. Thinner layers mean two things that are important for achieving higher densities:
- The width needed for controlled impedance lines is smaller on thinner layers
- The spacing between digital lines can be much smaller (well below the silly 3W rule limit) when ground is interleaved between signal layers
The other reason is the manufacturing process, which can fabricate well below sub-40 micron linewidths. However, if we were to decrease the linewidth, we would still be stuck with the 3W rule for trace spacing. The only way to enable spacing lower than a 3W limit is to place the ground plane closer to the traces, which requires thinner layers. I’ll discuss this more in an upcoming article on the effects of layer thickness in terms of signal integrity.
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