Designing a Four-layer PCB Stackup With No Plane Capacitance

In a number of previous articles, I have addressed the challenges encountered when designing boards with 16-layers and above. These are the kinds of complex PCBs found in high-end servers, switches, and the cloud titan products that support the ever-growing Internet needs.

However, many products don’t require these types of complex boards with high layer count. One example is the tens of millions of four-layer PCB motherboards manufactured each year for PCs and other comparatively low-cost products, such as Microsoft’s Xbox™ products. At first glance, it might seem that designing a 4-layer PCB should be an easy task, but just like any other board, it requires the right kind of layout and stack-up. In addition, there are particular challenges when it comes to designing a four-layer PCB stackup with or without plane capacitance. Since high plane capacitance is not available on a four-layer PCB without adjacent power and ground planes, other approaches must be utilized. This article describes how a four-layer PCB stackup is best designed along with how the lack of plane capacitance is handled.

The ABCs of a Four-layer PCB Stackup

Two-Layer Boards

Before there were four-layer PCBs, there were two-layer logic boards, as shown in Figure 1. These boards satisfied electronic needs quite well, and they were widely used before things were fast enough that required the low inductance connections achieved with planes.

Four-Layer PCBs

Four-layer PCBs have been the workhorse of computers and games for 40 years. From day one, PC motherboards have been four layers. And the need for four-layer boards will only continue to expand as more consumer-oriented products are developed.

The technical aspects that drive a four-layer PCB design are:

• Two good planes that distribute power that are continuous (usually below the surface layers).
• Trace layers that are close to those planes so that crosstalk and impedance can be controlled.

The key economic and business factors in creating a four-layer PCB is to manufacture it in huge quantities (factors of millions) at the lowest cost possible. These volumes are necessary because huge amounts of money have to be spent on creating the tooling that will be necessary to build the boards. The key benefits of four-layer boards include:

• Four-layer boards readily lend themselves to mass lamination techniques that use 36” x 48” panels.
• The imaging for the inside layers, which are just planes, is done with glass exposure plates instead of film. This makes the tooling more durable and more mechanically stable.
• After the inside layers are printed and etched, prepreg and foil are placed outside the laminate.
• Around the outside of each board on the 36” x 48” panel, there are small fiducials. The copper on the top of the boards is skived away so that the fiducials are visible, and the drill can be aligned to the pattern that is inside the boards. As a result, there is no need to worry about runout errors across the very large panels.

The Design Perspective

From the design perspective, the four-layer PCB stackup shown in Figure 2 is pretty straightforward. The elements to keep in mind include:

• The two outer layers are signal layers.
• The two middle layers are Vdd and ground.
• The distance between each signal layer and the plane below it is set to 4 or 5 mils to control impedance and crosstalk.
  • This distance forces the two plane layers to be very far apart—40 mils or more.
  • The plane capacitance at 40-mil spacing is minuscule compared to what it would be if the planes were adjacent (factor 10 lower).
    • The needed high-quality capacitance is on-die and on-package (more about this later).

Other factors about four-layer boards to keep in mind include:

• 40+ mils thickness is more than enough to make a board rigid.
• With a four-layer board, the routing rules for high speed signals are stricter because you can’t change layers without risk of creating an impedance discontinuity.
  • There has to be a team effort between the people who pin out the IC, the people who pin out the package, and the people who design the board. This has to be negotiated between these three groups.
  • All high speed signals would have to begin and end on the same layer. Figure 3 is a photo of a four-layer board section with all of the signals running in the top surface layer.

• The vias on a four-layer PCB are straight through-hole vias. These vias are plugged so that no contaminates can go from one side of the board to another. This type of contamination can cause pin-to-pin leakage under a BGA that cannot be cleaned and results in the whole assembly being thrown away.
  • Blind vias on a four-layer board are unnecessary because they would only be making the connection from the vias to the first power plane.
  • Blind vias make the cost of the board go up.

What About the Lack of Plane Capacitance?

As can be seen in Figure 4, and as noted above, the interplane capacitance on a PC motherboard with a 40-mil spacing is minuscule (about 5 pF square inch of plane capacitance). But a source of high quality (low inductance) capacitance is required to provide current to charge up the data and address lines.

This capacitance is provided by integrating large amounts of capacitance onto the IC die itself or in the component package. This same low inductance capacitance is the path by which return currents find their way from one plane to another when a signal changes layers. When this is absent, signals need to be routed from point to point while staying on the same signal layer.

Examples of the on-die capacitance of components and memory modules include:

• A DDR2 die has more than 100 pF per I/O pin built in to supply the charge to the lines being driven.
• A power PC IC has more than 200 pF per I/O pin built in to supply charge when driving single-ended lines.
• A power PC IC has on the order of 50 nF built in to supply the charge to the core as it changes from sleep mode to all on-active.
• The custom IC processor designed for the next-generation Blue Gene supercomputer, which has a 512 bit-wide memory bus, has 190 nF of on-die capacitance to support the transient.

What About Four-layer PCBs with Wide Buses?

Initially, the case for plane capacitance was necessary to support large, single-ended switching transients such as those involved in memory subsystems. However, with today’s wide buses, the following factors must be kept in mind.

• As noted above, on a four-layer board with signal/ground/power/signal stackup, there is very low plane capacitance.
• The only “return path” for signals changing layers is the discrete capacitors that function poorly at the frequencies involved in fast data buses.
  • As a result, signals must remain on the same signal layer for the entire path length.
• ICs that don’t have on-die capacitance to support fast switching edges will perform poorly on four-layer PCBs, resulting in systems that experience “flaky” operation and high EMI.
• As a result of the preceding, a combination of on-die and on-package capacitance is required and the following apply:
• With 130 nanometer and smaller IC geometries, the current inside the IC or core can often be reach tens of Amperes in as short as 15 ps.
  • Current transients of this magnitude and speed cannot be supported by capacitance on the PCB due to the inductance of the package balls and vias.
• Combining ultra-low inductance capacitors mounted on a well-designed BGA package with on-die capacitance solves this problem.

Summary:

Four-layer PCBs are a mainstay of the computer and game console products industries. The successful design of a four-layer PCB stackup, layout, and routing is based on valid design rules, and there are ways to provide capacitance when internal plane layers do not provide sufficient interplane capacitance. This capacitance is provided on-die on the ICs or through a combination of on-die and on-package configurations.

Talk to an Altium expert today to learn more or discover more about planning your multilayer PCB stackup in Altium Designer®.

References:

1. Ritchey, Lee W., and Zasio, John J., “Right The First Time, A Practical Handbook on High Speed PCB and System Design,” Volume 2.
2. Ritchey, Lee W., Course Slides, “2-Day Signal Integrity and High-Speed System Design,” training class.