I can’t think of a single product I’ve built that doesn’t require capacitors. We often talk a lot about effective series inductance (ESL) in capacitors and its effects on power integrity. What about effective series resistance (ESR)? Is there a technique you can use to determine the appropriate level of resistance, and can you use ESR to your advantage?
Like many answers to important engineering questions, the answer is “it depends.” One type of capacitor you can use to take advantage of series resistance in capacitors is a controlled ESR capacitor. Depending on the impedance target you need to hit and the required lowimpedance bandwidth in your highspeed PDN, you might find these components useful as decoupling capacitors. However, don’t rely on these components to be the endall solution to your PDN impedance problems; smart component selection and simulation will give you the best chance of producing a flat PDN impedance spectrum for your highspeed/highfrequency design.
A controlledESR capacitor has repeatable ESR value as seen at the leads on the component. Typically, when someone refers to a “controlled ESR capacitor,” they’re referring to a small case capacitor with an ESR value in the hundreds of mOhm range. To be more specific, a component manufacturer that specifies a certain capacitor as controlled ESR is telling you that they can guarantee a minimum ESR value, as well as the more precise nominal or maximum ESR value you’ll find in datasheets.
Note that very large capacitors might have large ESR values, something that is typical (and useful) in power electronics; we’re not referring to these large capacitance, large case components when we refer to controlled ESR capacitors. Some multilayer ceramic capacitors (MLCCs) are marketed as controlled ESR capacitors, but the term could technically apply to any type of capacitor.
There’s a good reason controlledESR capacitors are often overlooked when selecting components for decoupling, particularly at high frequencies. When we talk about PDN impedance, we always aim for ensuring a low impedance in order to minimize the amplitude of any transient response in the PDN whenever switching events occur in digital components. Target PDN impedance values can reach sub10 mOhm levels, yet a controlled ESR capacitor can contribute on the order of hundreds of mOhms impedance to the PDN, something we generally wouldn’t want. However, it opens up the possibility of two possible design goals:
The second design goal is nice, but not always practical. There are several reasons for this, which I’ll discuss in the next section.
First, let’s look at the typical circuit model for a capacitor and how multiple capacitors are linked in the PDN on a PCB. The schematic sheet below shows a circuit model for a group of 4 capacitors in parallel. For the moment, let’s assume that they all have the same ESL and ESR values, but different capacitances as shown below:
Here, we have capacitors with 50 mOhms ESR, which is certainly within a range that is used to market controlled ESR capacitors. The important point from this schematic is that the PDN can be roughly modeled as a set of RLC networks in parallel. If you remember your basic AC circuits classes, then you’ll know that the resistance in an RLC network (or the ESR in a controlled ESR capacitor) will determine the Qfactor of the network: a capacitor with a higher ESR value will contribute higher impedance offresonance, but it will have a flatter impedance within its bandwidth.
Just from thinking about the ESR value and realizing that you have a bunch of parallel RLC networks in a PDN, it’s possible to predict where you’ll need to add a bank of controlled ESR capacitors vs. lowESR capacitors to flatten out the impedance of the PDN. Assuming none of the selfresonance frequencies overlap, we will in general see multiple peaks and valleys in the PDN impedance spectrum (antiresonances and resonances, respectively), which correspond to the poles and zeros in the PDN. If you have N number of unique capacitors, then you can expect to have N poles in the PDN. A controlled ESR capacitor with sufficiently high ESR could eliminate one of these peaks.
Just to see what happens if we have multiple capacitors with different ESR values, let’s look at an example. In the graph below, I’m showing PDN impedance simulation results with banks of four different capacitors while scanning through various ESR values.




















The ESR values of C2 and C3 were varied from 50 mOhms to 750 mOhms. As we can see below, increasing the ESR value for these capacitors has the effect of smoothing out portions of the PDN impedance spectrum.
The effect is interesting because we can see that it spans an entire decade in terms of frequency. Note that the smoothing can be seen from 10 MHz to 100 MHz. The graph above only captures the effects from the capacitors, it doesn’t contain any information about plane capacitance, plane resonances, or plane/trace/rail inductance in the board.
You could certainly take the complex PDN impedance as a transfer function and use it to calculate the voltage fluctuation seen at the power pins of various components in your PDN. However, because we have, in general, an Npole problem, the ESR values required for stability do not necessarily obey a simple equation. I would approach this as a firstorder eigenvalue problem and calculate the stability criteria for each portion of the PDN, something which is mathheavy. While you could certainly write a MATLAB script to automate this and give you a view of the transient response in the time domain, I would instead focus on staying below your target PDN impedance by strategically adding more capacitors to the PDN to increase the capacitance.
One point to note is that you don't need to have a flat impedance spectrum, and in all practical considerations, you'll never get it perfectly flat. Instead, focus on reducing peaks below your target, and make sure you test your proposed design.
Anytime you need to damp a transient oscillation, which is driven by L and C elements in a circuit, the typical solution is to add resistance. While it is not normally communicated in this way, the optimal solution is to critically dampen the transient response such that the edge rate of any transient response is optimally fast, yet the oscillation is suppressed. Too much resistance, and you have slow rise time due to overdamping.
In the above results, we looked at the effects on impedance, not on the timedomain transient response. However, the results are clear: adding some resistance through the use of controlled ESR capacitors smooths out the PDN impedance, which is exactly what we would like in a digital PDN. If you look at the results in my earlier article on capacitor optimization, you can simply add more capacitors in parallel to move the entire PDN impedance curve down to lower values.
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