Developing a PCB Testing Procedure For New Designs

As noted in several of my previous articles, at Speeding Edge we are big proponents of putting test structures into PCBs. The impetus for incorporating these structures covers a wide variety of topics—it’s a new design; you’re using new component technology; a new laminate or a new fabricator to name a few.

There are many critical performance characteristics required of today’s electronic products. They operate at high frequencies, move enormous amounts of data, and they do it faster than ever before. This puts a huge amount of pressure on product developers to make sure their designs check all the boxes, work as prototypes as well as in volume production, and meet critical cost and product delivery requirements.

Given all these parameters, it’s a wise technical and business decision to develop a PCB testing procedure before fabricating a new design. Test structures on a PCB can be used prior to loading the board with components, which will help ensure the board will operate as specified and as built.

Test Structures in PCBs

The things that create the impetus for building test structures on a board are based on the following:

• Assuming that boards coming in from a manufacturer are “good” just because the manufacturer says they are.
• Even when you are dealing with a reputable manufacturer, there are places within the manufacturing process where things can go wrong such as:
• The layers are in the wrong order (more about this below).
• The impedance is incorrect.
• The wrong laminate was used or the fabricator substituted your specified laminate with a replacement under the guise of “saving you money.”
• The glass weave in the laminate is wrong causing skew.
• This is a huge issue with products that have really high data rates.
• The skew problem won’t be evident until the assembly process.

As noted above, it’s an imperative that the layer stackup in the board is validated through use of stacking stripes that are on the edges of the board. This may seem to be a simple issue or mundane practice, but it is one that can result in dire consequences if it is not done. If board layers are out of order, there is no easy fix and there can be significant cost and schedule hits as the only option is to scrap the boards and start all over again.

Figure 1 depicts a stacking stripe test structure. The strips of copper used in the structure are plotted in such a way that when the PCB is cut from the panel, the strips are visible to the naked eye. The strip in each layer gets longer than the one above. This makes it possible to determine that all the layers are in the correct order by simply seeing that the stair steps get longer going down into each layer of the PCB.

There are many places in the design and fabrication process where the order of the layers can be mishandled. One is in preparation of the photo-tools and stencils used to etch the PCB layers. Another can occur when laying up of the individual layers as part of the lamination process. Obviously, the greater the number of layers in your board, the more important the stacking stripe test structures become.

Figure 2 shows an example of a failure detected through the use of test structures. Layer 11 is where layer 22 should be. Both are power planes. The out of place layer is indicated with stacking stripes, which are visible on the side of the board.

In this instance, all the impedances were correct because the layers that were swapped contained power and ground planes. Additional failures we have detected with test structures include an assembly where the incorrect bypass capacitors were called out on the bill of materials. Stacking stripes can also be used to detect incorrect impedance values.

Figure 3 shows an enlarged view of an actual set of stacking stripes, where the glass fibers in each dielectric layer, the copper thickness, and 5-mil traces can be seen protruding from the PCB.

A PCB Testing Procedure

As with any process, there are specific steps to be taken on the PCB prior to it being loaded with components. This PCB testing procedure goes beyond in-circuit testing. These steps include:

1. Taking the stack up drawing and recording the actual impedance of each signal layer next to the calculated impedance. (Make sure to measure this with a 125-175 pSec edge.)
2. Polishing the stacking stripes to make sure they are crisp. Next, to preserve them they should be covered with clear lacquer.
3. Making sure the stripe in each layer is longer than the one above.
4. Using a microscope with a scale in it, measuring the thickness of each dielectric layer and recording this information on the stackup drawing.
5. Measuring and recording the thickness of each copper layer.
6. Measuring the width of the trace that is next to each stacking strip and recording it.
7. With an ordinary capacitance meter, measuring the plane capacitance of each power supply voltage and comparing that information to that which was calculated.
8. With a network analyzer or a spectrum analyzer with a tracking signal generator, sweeping the impedance vs. frequency for each power supply voltage. Then, the scope images of each sweep should be compared against one another. (The method for doing this is described in the Reference 1, Volume 2 at the end of this article.)
9. The foregoing steps 1-7 should be performed with every new lot of PCBs that are received and every PCB should be checked to verify that the stacking stripes are in the correct order as noted in Step 3 above.

If the foregoing measurements are within specification, the next task involves verifying that the bypass capacitor population creates the proper impedance vs frequency response for each power supply voltage. This is done by sending one PCB out to be loaded with only the bypass capacitors and then performing the following tests:

1. Sweeping the impedance vs. frequency of each power supply voltage as noted in step 8 above and comparing that information to the predicted impedance vs. frequency. If the impedance goals have been met, the PCBs can be sent out for final assembly. If there are “impedance holes,” it’s necessary to recalculate the population of capacitors needed to eliminate the holes.
2. If required, performing hi pot tests.
3. Listing the bypass capacitors used for each voltage with the parameters shown in Table 1.

After the foregoing, the following tests are performed to examine the performance of the IC packages and the power supplies under worst-case conditions.

1. Using the appropriate software code, cause any processors to go from standby mode to active mode at the slowest and fastest rate that will occur in operation. It’s imperative to monitor Vdd for the processor core and record the worst-case ripple. The resulting scope picture should be retained. It’s also important to verify that the measured ripple on the PDN is within the design spec.
2. Using the appropriate software code, cause the widest data busses to switch first from all 0 to all 1 and then from all 1 to all 0. Again, the ripple on Vdd is monitored; the scope picture is retained and the ripple is verified against the design spec.
3. Using the same code used in step 2 above, it’s important to measure the Vcc and ground bounce by attaching a scope to a quiet output that shares the same power rails inside the IC package with the data bus being switched. Here too, the scope pictures should be retained and the Vcc and ground bounce is verified to be within the requirements of the design spec.

Special Tests for Backplanes

1. As a rule, backplanes don’t have power supplies, other than a raw DC voltage such as 48 V. However, they are likely to have special plane capacitors on selected lines to control EMI. The test steps used for backplanes include: Performing steps 1-6 for bare unloaded PCBs as noted above.
2. Measuring the value of each signal that has an embedded capacitor. This is done with an ordinary capacitance meter and the result is compared to the design goals.
3. Performing hi pot tests as needed.

Other Special Tests

Test traces of varying lengths: On some PCBs there may be two test traces of varying length in the same layer. Measuring the time delay on each can be used to calculate the velocity by taking the difference in time and dividing it by the difference in length. This enables the calculation of the effective dielectric constant for that layer.

DC voltage drops: On PCBs with very high currents, it is advisable to take a multimeter and run a voltage drop profile from the terminals of the regulator to the farthest load to ensure the DC voltage drops are within limits. As noted in previous articles, a lot of today’s designs can’t tolerate very much voltage sag. Since there is not a lot of margin to begin with, there doesn’t have to be very much variance before limits have been exceeded.

Summary

There are several valid reasons for placing test structures as part of a PCB testing procedure. These structures serve a number of purposes, including ensuring layers are in the correct order; ensuring the copper layer thicknesses and trace widths are correct; ensuring that the capacitance power supply voltages are correct; making sure the impedance vs. frequency for each power supply voltage is correct and ensuring that voltage drops are within the proper tolerance range.

Would you like to find out more about how Altium can help you with your next PCB design? Talk to an expert at Altium.

References

1. Ritchey, Lee W. and Zasio, John J. “Right The First Time, A Practical Handbook on High Speed PCB and System Design, Volumes 1 and 2.