Should You Remove Ground Below Impedance Matching Networks?

Zachariah Peterson
|  Created: May 15, 2023  |  Updated: May 19, 2024
Should You Remove Ground Below Impedance Matching Networks?

In an impedance matching network, the goal is to tailor the resistance, capacitance, and inductance of the circuit such that power or voltage transfer to a load is maximized. Controlling these factors around an impedance matching circuit in a PCB is all about placement and sizing of traces and ground, as well as matching these to the pads on your discrete components. To eliminate additional parasitics from the pad size and traces connecting to these components, sometimes you need to modify where ground is placed around the impedance matching circuit components.

Why Ground Might Be Removed

In many systems, it is common to build impedance matching circuits from discrete components, usually SMD passives. Sometimes, when ground is cleared below an impedance matching network, we are not completely eliminating ground below these circuits. This is because the feedlines coming into and out of the circuit need to be a target impedance (usually 50 Ohms), so ground is still needed in the device. Your options for modifying the placement of ground include:

The reason for doing this is quite simple: we want to reduce the amount of additional parasitic capacitance and inductance around the impedance matching circuit components. It is well-known that parasitics modify the performance of real passives in high-frequency circuits, creating a limit on the return loss expected at each port. Unfortunately, you can never get rid of this pad/trace capacitance on SMD components, you can only try to minimize so that the circuit operates as close as possible to the theoretical performance.

Therefore, in some cases, it could make sense to modify where ground is placed around these components. We want to ensure that the sizes of the pads and traces on the components do not create excessive additional parasitic capacitance that modifies the impedance of the capacitors and inductors in the impedance matching network.

Cleared Ground in an RF PCB Layout

The example below from our earlier nRF52 project shows how ground can be cleared; the pi filter matching circuit is shown below. Note that this matches well with the guidelines from Nordic’s nRF52 reference board. Here, coplanar ground is used on L1, and there is uniform ground below the impedance matching network on L6. Ground is only cleared below the matching network region, and only on L2-L5.

impedance matching network ground

If we look above, the component pads have some capacitance back to ground; this adds capacitance to the discrete capacitors in the impedance matching circuit. The same idea applies to inductance involving ground and the lead inductance of the components. How do we clear out ground without impacting the line impedance?

First, we can use coplanar ground around the traces to set their characteristic impedance to the target impedance matching the chip’s output. A polygon cutout is used below the feedline only on the internal layers. The bottom layer has uniform copper pour below the impedance matching circuit. The top layer also has copper pour, but the standard clearance rule has been enforced around the traces and pads on these nets in order to set the characteristic impedance of the traces to the target value.

Now let’s look at an example given the example RF layout shown above.

How Large is the Deviation?

To determine the deviation, we can compare the theoretical case to the real case. Initially, we have a 0402 capacitor and 0603 inductor. If we had the ground directly below these pads and the connecting traces, the parasitics on the capacitor would be about 3 pF/inch and 7.5 nH/inch on Dk = 4 laminate. With the coplanar configuration and ground only on L6 shown above, the parasitics drop to about 2.75 pF/inch and 6.9 nH/inch. We can perform similar calculations for the inductor pads.

The total parasitic capacitance and inductance given the distributed element values above are summarized below. Note that this only accounts for the traces around the components and the pads; it does not account for the self-inductance of the package leads.


GND on L2

GND on L6

0402 capacitor and 0603 inductor

0.5652 pF to GND

0.4388 pF to GND

0402 capacitor and inductor

0.4461 pF to GND

0.4090 pF to GND


A simple change in ground location from L2 to L6 reduces the parasitic capacitance by 22.4%. With these values, it’s now possible to include these parasitics in a simulation and determine their effect on the output impedance of the network.

The inductance calculation is a bit more complicated because it involves some loop inductance around the pads as well as lead inductance, both of which may not be so easy to determine. The trace self inductance in series with the inductor also plays a role in determining the total inductance. In general, it is not safe to just assume that the modified inductance compensates for the modified capacitance.

Note above that I have included an option for all 0402 components instead of the 0603 inductor. We can see that there is a reduction in the parasitic capacitance from the pads and traces simply because the 0603 inductor has larger pads than the 0402 inductor. This modified example is shown below.

impedance matching network ground

We get slightly less parasitic capacitance with this arrangement, but it’s not much; it’s only a 6.8% reduction compared to the mixed package sizes. In all of these different cases, it’s important to now determine whether this will matter in your particular system.

Does This Deviation Matter?

To determine whether or not this parasitic capacitance and inductance are important, we have to compare the values to the component values placed in the PCB layout.

In the nRF52 example above, the capacitor values used in the matching network were 1.2 pF. With additional capacitance of 0.4388 pF, this network acts like it has total capacitance of 2.8388 pF. The result is about 5 Ohms of impedance reduction from the target impedance. Assume for a moment that the circuit with no parasitics was perfectly matched to 50 Ohms; if we were using this real impedance matching network to transform to a target impedance of 50 Ohms, the resulting return loss would be S11 = -27.5 dB.

What if our capacitors were 1.2 nF? In this case the additional parasitic capacitance is barely noticeable and would have no effect in our pi filter. In general, if the additional parasitic capacitance is much smaller than the discrete capacitance, then it can be ignored; the same idea applies to the inductance.

Note that this design with the 0603 inductor was tested on a client board and it was found that it operates within spec, so I would be comfortable using the same network in this project. However, the points outlined above should be considered if you want to use this design in your own projects. The above concepts are quite important for practical components operating in the 1-6 GHz range where impedance matching networks are required.

The reason ground might be removed more often in systems operating in the 1-6 GHz range is that the capacitors used in these impedance matching networks can be quite small (~1 pF). The ~1 pF of discrete capacitance in the network is similar to the expected parasitic capacitance around a 50 Ohm line on Dk ~ 4 laminate. This parasitic capacitance essentially exists in parallel with the discrete capacitance, and together this could modify the matching condition.

Where’s the Matching Network at Higher Frequencies?

At frequencies higher than WiFi, you might not see any impedance matching networks on your RF interconnects that are intended to operate at 50 Ohms. There are two important reasons for this:

  • Most RF ICs will incorporate their impedance matching network onto the die
  • RF circuits or antennas will tend to be built specifically to operate at the target impedance.

Take radar transceivers as an example. There are millions of automobiles and specialty sensors that use these transceivers, and in all of those boards, you won’t see any impedance matching networks on the PCB. In these systems, we care about parasitic capacitance around the PCB, and in particular on high power RF amplifiers, but we aren’t placing impedance matching networks with small discrete components on the PCB, and we certainly aren’t clearing ground below drive and receive pins.

Now consider the series-fed patch antenna operating at ~77-78 GHz shown below. This antenna is intentionally designed to operate at 50 Ohms. Normally an individual patch antenna (or simple printed microstrip antenna) could have an input impedance of 200-300 Ohms. The reason the below antenna has 50 Ohms input impedance is due to its small size and through the use of fractional wavelength matching lines to link the patches. This also gives the wide emission bandwidth as shown in the return loss plot below.

impedance matching networks

I bring up these examples to illustrate the following important point: don’t be surprised if you don’t see an impedance matching network built from discrete components when your RF system operates at very high frequencies. These components will generally include ground below their TX and RX pins, as well as a more complex signal launch located around the mounting pin on the PCB.

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About Author

About Author

Zachariah Peterson has an extensive technical background in academia and industry. He currently provides research, design, and marketing services to companies in the electronics industry. Prior to working in the PCB industry, he taught at Portland State University and conducted research on random laser theory, materials, and stability. His background in scientific research spans topics in nanoparticle lasers, electronic and optoelectronic semiconductor devices, environmental sensors, and stochastics. His work has been published in over a dozen peer-reviewed journals and conference proceedings, and he has written 2500+ technical articles on PCB design for a number of companies. He is a member of IEEE Photonics Society, IEEE Electronics Packaging Society, American Physical Society, and the Printed Circuit Engineering Association (PCEA). He previously served as a voting member on the INCITS Quantum Computing Technical Advisory Committee working on technical standards for quantum electronics, and he currently serves on the IEEE P3186 Working Group focused on Port Interface Representing Photonic Signals Using SPICE-class Circuit Simulators.

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