Even complex systems like this are easy to design thanks to ethernet layout routing standards
Ethernet over copper is likely part of the backbone of your office building’s networking infrastructure. Thankfully, Ethernet routing standards make it easy for designers to create everything from complex networking equipment to single-board computers for any application. The overall architecture for creating Ethernet-capable devices is deceptively simple, but certain rules should be followed to ensure signal integrity.
High-level Ethernet Layout Routing and Architecture
Within the IEEE 802 standards, Ethernet devices contain three primary elements, all of which must be routed together in a specific manner. The Medium access control (MAC) portion is typically integrated into the processor of the device (FPGA, ASIC, MCU, or other component). The MAC provides control over determining destination addressing, sends along its own address to receive data, and duplexes and assembles data into packets for transmission to another device.
The next stage in Ethernet layout routing is the physical layer (PHY). This is typically an integrated circuit that converts the digital data from the MAC into analog signals for transmission down copper or optical fiber. The standard routing protocols for Ethernet (MII and RMII) are compatible with 10Base-T and 100Base-TX, although similar routing standards are designed for 1 Gbps and higher data rates. The output from the PHY connects to an RJ-45 connector. These connectors require a specific termination scheme (see below) to preserve signal integrity.
With optical fiber networks, the output from the PHY connects to a separate fiber transmitter/receiver with its own layout rules. Commercially available transceivers are available with edge connectors or other connectors. This allows these transmitter/receiver modules to be swappable, ideally without taking apart an entire unit (e.g., hot-swappable interfaces).
Fiber optic media converter with an RJ-45 connector
Routing between the MAC and PHY follows either the MII or RMII routing standards with point-to-point topology. The primary difference between these two routing standards is the number of signals required to interface between the MAC and each PHY chip. In a multi-port device, two signals from the MAC can be shared among multiple PHY chips, while another 16 signals (MII routing) or 6-7 signals (RMII routing) are required per PHY chip. Obviously, the number of signals required to reach a large number of PHY chips quickly becomes unmanageable, thus RMII was developed to reduce the total number of signals by a factor of 2.
The final important element is a clock that is used to trigger signal transmit and receive functions between the MAC and the PHY. In MII, a 2.5 MHz clock is used for 10 Mbps data rates, while a 25 MHz clock is used for 100 Mbps. In RMII, a 50 MHz clock is used for both data rates. All routes should be placed on a single layer within the device with precise length matching. TTL is used in these devices, thus length matching can be rather generous compared to other routing standards for computer peripherals.
Routing and Termination for RJ-45 Connectors
The routing requirements between the PHY chip and RJ-45 connectors are much more strict. TX and RX lines are routed as differential pairs, and these traces must be length matched and symmetric. Remember that this circuit and associated traces are carrying analog signals, thus they need to be routed over an analog ground plane. Make sure to design an appropriate mixed signal ground plane in your device.
There is also a specific termination circuit that must be placed between the PHY and the RJ-45 connector, commonly termed “magnetics” within the Ethernet layout routing standards. A magnetics termination circuit involves four transformers for a single RF-45 connector, two on each RX and TX differential pair.
One transformer is placed as a common mode choke, while the other is placed downstream (towards the connector). Tapped ferritic transformers with 1:1 turns ratio are normally used to provide the required common mode noise rejection in the TX and RX differential pairs that connect the termination circuit to the PHY. This also allows any required DC bias to pass to the termination circuit (e.g., to power any LED indicator lights in the connector).
Some application notes will recommend not placing a ground plane beneath the differential pairs. However, EMI susceptibility can be reduced by connecting common mode capacitors between the RX/TX traces and ground, in which case the analog ground plane should extend beneath these differential pairs. The differential pairs should be impedance matched throughout the termination circuits, and the common method is to include a Thevenin network or a pull up resistor near the PHY. In this case, a portion of the power plane will need to appear near the pull-up resistor.
Example industrial-grade magnetics termination circuit for an RJ-45 connector
Note that some RJ-45 connectors include this second transformer or both transformers as part of an integrated magnetics circuit. Always check the datasheets for integrated connectors to see what other components need to be added to complete the termination circuit. If these transformers and associated passives are not integrated, Ethernet transformer modules are also available as discrete components (usually in SMT packages). These discrete modules provide better ESD protection as there will be larger separation between each portion of the system.
Stackup for Ethernet-Capable Boards
Finally, we can’t ignore the layer stack for Ethernet-capable PCBs. 2-layer or 4-layer stacks are generally used, although you could certainly use a higher layer count. In lower layer counts, power islands are generally used with a ground plane on the same layer. These planes should be decoupled with an appropriate capacitor.
Copper pour can also appear on the surface layer to provide extra shielding against EMI, which is a desirable choice if your device includes a WiFi module or other RF circuits. Note that if you place ground pour on the surface layer, it should be connected to the lower ground layer with a periodic array of vias. Only place copper pour on the surface directly over a ground plane in the next layer.
When routing on the surface layer, you may need to route a signal over a ground plane and a power island for a single interconnect. This is generally a bad idea in any device as the portion of the trace that is not placed over a reference plane can radiate strongly, and the overall circuit it forms will have large loop inductance. To provide a return path and properly switch reference planes during routing, place a small capacitor (usually ~10 nF) between the ground plane and the power island that runs parallel to the trace.
When you use a design platform like Altium Designer, you’ll have all the routing tools you need to design Ethernet and fiber optic-capable networking devices with ease. The schematic design, layout, routing, and many more features are all accessible within a single unified design interface. You’ll also have access to the industry’s best signal integrity and documentation features in a single program.
About the AuthorMore Content by Zachariah Peterson