LVDS PCB Layout Guidelines for Ensuring Signal Integrity

Zachariah Peterson
|  Created: May 5, 2019  |  Updated: February 16, 2022
LVDS PCB Layout Guidelines

When you first get started in high-speed PCB design, you'll spend a lot of time encountering and understanding an alphabet soup of acronyms. MIPI, USB, PCIe interface, SATA PCB layout... the list of acronyms used to name high-speed digital interfaces is long. Low-voltage differential signaling (LVDS) is an older interface that was standardized for differential data transfer at high speeds, but it remains in use today for a variety of imaging and video applications. More specifically, it is used in many LCD-TVs, computer peripherals, infotainment systems, and notebook/tablet computers. 

If you're unfamiliar with this specification or you just need a refresher, we'll look at some of the basic LVDS guidelines to ensure signal integrity in your high speed PCB.

The Foundation: Understanding the LVDS Specification

Low-voltage differential signaling (LVDS) is codified in the TIA/EIA-644 standard and is a serial signaling protocol. Probably the most common electrical uses for LVDS are as an physical layer for SerDes links, long-reach channels in backplanes, or board-to-board connections. It's important to note that the TIA/EIA-644 does not define LVDS as an interface, it is a physical layer within the OSI model. In other words, this only defines a physical and electrical specification that fits within an interface standard. For example, LVDS is used as the physical layer for routing between PCIe interfaces.

Interface Implementation

The image below shows a schematic of an LVDS link; assume channel losses are 0 dB for the moment. The diagram below (or a version of it) can be found on many websites, including Wikipedia. I'd like to note that this diagram is only correct for DC-coupled differential pairs. The diagram unintentionally implies that the termination resistor exists external to the receiver component. This is not actually the case; the termination resistor (if that is what is specifically used) or the overall receiver circuit could be entirely on the receiver component die.

LVDS buffer circuit
LVDS channel schematic and voltage levels.

On the left side of the image we have the line being driven by a differential buffer circuit, which passes a 3.5 mA current onto a 100 Ohm differential pair. On the right side, the receiver reads out the differential voltage, which is being measured against some common mode DC offset. Bidirectional communication can be implemented as well in half-duplex or full duplex mode if the transceiver components can accept this (see the SN65LVDS180D for an example), or parallel receiver/transmitter channels in dual simplex mode.

LVDS Termination and Coupling

The above situation is idealized and only considers DC coupling, where there is a direct connection to the transmission line, or the connection is made through resistors at the driver. It does not consider filtering of common-mode noise at high frequencies, the need to set a bias offset in differential termination, or the fact that the receiver DC offset may be different from the driver DC offset. It also does not account for length mismatch and would not practically account for the wide timing window because there is no voltage source to set the receiver's bias offset. Therefore the above circuit only works when there is no time mismatch.

The alternative method for driving LVDS signal levels on a differential interface is to use AC coupling, similar to what you might see on PCIe with coupling capacitors, followed by applying double termination at the required single-ended impedance. The advantages of AC coupling include isolation from power surges (such as in automotive), the ability to set different common-mode offsets at the driver and receiver ends, and the ability to translate between different component families by choosing the appropriate offset.

The circuit below shows an example where AC coupling is implemented on each trace in the LVDS differential pair. This particular circuit with the capacitor connected between two termination resistors relies on terminating directly to the single-ended impedance (odd-mode) of each trace rather than the differential value.

LVDS receiver termination
Example LVDS receiver termination circuit with AC coupling.

In the above circuit, we select the design based on the following points:

  • The coupling caps need to be large enough to remove DC offset from the driver.
  • VBB is set internally in the LVDS receiver and will be equal to the DC offset in the received differential signal.
  • The shunt cap in the receiver side needs to be large enough to shunt the maximum amount of common-mode noise to ground. A cap on the order of 1 uF is typical.
  • Depending on which data sheet you are looking at, you may see the receiver side of the link pulled up/down to set the required logic levels above/below the VBB offset.

Whether the channel would be implemented with the above AC circuit or some other variant depends on whether the receiver is self-biased, includes on-die termination, and whether the source is also terminated with its own parallel source resistor. Highly integrated components will place all of this on the die and will allow you to just route everything without additional placement as long as the logic levels are matched between the driver and receiver. Make sure to review the datasheets for your driver and receiver pair carefully before you finalize your circuit.

Physical Layer Specification

As LVDS is a physical layer specification and not a component interface specification, it only carries specific requirements in the following areas:

  • Signal swing: The swing across the 100 Ohm termination resistor is 350 mV, although one should note a different impedance may be used in an LVDS link.
  • Embedded clocking and encoding: LVDS does not require a specific encoding scheme, but this is allowed under the standard. 8b/10b encoding is commonly used.
  • DC offset: A common DC offset in LVDS Rx/Tx components is 1.2 V. 
  • Topology: Single links, bi-directional links, and multidrop topology are allowed. In particular, multi-drop topology is common in backplane buses and cascaded board-to-board connections.
  • Data rate: LVDS can theoretically support any data rate as long as signals are recoverable at the receiver. LVDS is typically used for serial data rates from 400 Mbps to above 3 Gbps.
  • Media: Like Ethernet, LVDS is media-independent; it can be used in traces on a PCB or on cables with specified impedance.

From the above list, we see that LVDS is simply a typical high speed differential channel with flexible data rate, topology, signal swing, and rise time. As this physical layer specification is used with a range of data rates, there is no specific signal rise time; the rise time is generally less than 1 ns. With these points in mind, we have everything needed to start designing a board to work with LVDS.

LVDS PCB Layout Guidelines

Doing LVDS PCB layout successfully requires following some of the same guidelines you'd follow with other high speed signals. I'd say the only difference is in how you view losses on the board or on a cable carrying LVDS signals. The typical transmission distances ranges from several inches (chip-to-chip) to several meters for an LVDS SerDes link driving a cable between boards. On the PCB, LVDS channels have to be designed with controlled impedance but without interfering with other circuitry.

Gridding and Component Placement

LVDS links are high speed signals that are intended to have low EMI, but they can still induce crosstalk in other interconnects. Parallel LVDS links can also induce differential crosstalk in each other when switching at high speeds, so consider the spacing between differential pairs when planning your routing strategy. As with other high speed or mixed signal designs, it's a good idea to plan out a specific region of the board for LVDS channels so that they don't get too close to other circuitry.

PCB Stackup Design

Consider your PCB stackup design when planning a layout with LVDS links. Since LVDS needs impedance control, you'll want at least a 4-layer board with a thin dielectric on the outer sides. The two surface layers will be allocated to routing signal traces and/or placing components, and the interior layers should be power and ground layers. You can route LVDS signals on opposite sides of the board, and the internal plane layers will provide impedance control, but best practice is to hold the LVDS portion over the GND plane and not over the power plane.

If you're using a wide parallel bus specification, then you'll need a lot of space for routing and you might consider leaving enough layers for impedance-controlled striplines. If you're only routing a couple LVDS links (such as parallel RX/TX channels), you'll probably be fine with microstrips on a 4-layer board. Make sure to apply impedance control by setting the appropriate trace width in your routing tools.

A connector with specific LVDS PCB layout guidelines
Impedance control is essential when routing LVDS through a board-to-board connector.

Going further, some of your components that operate with LVDS signals (some display interfaces, for example) will require different power planes that are brought to different voltages. Some components will also require that you place ground islands on your surface layers to accommodate connectors or center pads on components. Keep these points in mind when planning the stackup and dividing up board real estate before routing.

Opt for Shorter Routing if Possible

On the PCB, LVDS routing uses low signaling swings that may need to be distinguished above a DC offset, so losses should be avoided. Long links will have greater attenuation due to dielectric losses and copper roughness/skin effect losses, which are manifested in insertion loss. Keeping links shorter ensures they see less loss compared to a longer link where insertion loss dominates. This leads to the next consideration that you won't often find in LVDS routing guidelines: how to accommodate higher signal bandwidths.

Consider the Signal Bandwidth and Losses

In shorter links, you now have the problem of return loss dominating your channels, and this will create a bandwidth-limiting effect that is normally seen in one of the S-parameter spectra. Although it's complicated, try to design the channel to have flat impedance and no dips in the insertion loss up to the interface's highest frequency as this will push the first lossy resonance as high as possible. The 

  • Short links: If links are short enough that return losses dominate, then flat impedance is the priority as this helps push return loss resonances as high as possible.
  • Long links: If an LVDS link is long enough that attenuation, then try to prevent any big dips in the insertion loss from arising. This is one reason we limit the via count on high speed differential links.

The latter case is most common and it illustrates the original intent of differential interfaces like LVDS. For very high data rate LVDS channels, you may need several GHz of bandwidth in the channel, which can be rather difficult due to dispersion in the PCB substrate and copper roughness dispersion. Take a look at this recent article on return loss to see an example of how channel bandwidth can become limited, particularly in short channels.

Length Matching

LVDS pairs should also be precisely length-matched to prevent excessive timing skew between signals in a pair. If you examine recommendations in LVDS interfaces in component datasheets, you'll find different allowable skew values. The requirements you might see in datasheets appear stringent, but the design rule regarding length tuning really depends on ensuring signal swings on each trace in an LVDS pair occur at the same instant at the receiver. As long as the two signal swings cross, then you the signal can be recovered at the receiver.

Eliminating skew is central to ensuring LVDS components can reject noise from environmental EMI, but pay attention to the delay matching requirement for your particular component and board. As LVDS components read the voltage difference between each end of the pair, any common mode noise induced in a differential pair should be suppressed during the signal swings on each trace as long as there is not excessive mode conversion.

Colored PCB traces on black background

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About Author

About Author

Zachariah Peterson has an extensive technical background in academia and industry. He currently provides research, design, and marketing services to companies in the electronics industry. Prior to working in the PCB industry, he taught at Portland State University and conducted research on random laser theory, materials, and stability. His background in scientific research spans topics in nanoparticle lasers, electronic and optoelectronic semiconductor devices, environmental sensors, and stochastics. His work has been published in over a dozen peer-reviewed journals and conference proceedings, and he has written 2000+ technical articles on PCB design for a number of companies. He is a member of IEEE Photonics Society, IEEE Electronics Packaging Society, American Physical Society, and the Printed Circuit Engineering Association (PCEA). He previously served as a voting member on the INCITS Quantum Computing Technical Advisory Committee working on technical standards for quantum electronics, and he currently serves on the IEEE P3186 Working Group focused on Port Interface Representing Photonic Signals Using SPICE-class Circuit Simulators.

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