Some LVDS PCB Layout Guidelines for Ensuring Signal Integrity
For me, arranging components on a PCB is like a fun puzzle. It’s something to do on a rainy day and can take the same type of trial and error approach. Working with a signalling standard like LVDS doesn’t have to be as difficult as a 1,000 piece puzzle if you know some basic design tips.
As a signalling standard used in many IoT devices and computer peripherals, designers should take some time to learn some LVDS PCB layout guidelines. This high speed, low voltage, and relatively noise-immune standard will likely become more popular in consumer devices and military equipment. Components that use LVDS signalling take some special layout considerations that aren’t always found in datasheets.
The Foundation: Your LVDS PCB Stackup
LVDS-capable PCBs must have the right stackup as this will determine how you layout your components and traces. Depending on the application for your board, you’ll need at least 4 layers in your stack. The two surface layers will be allocated to routing signal traces and/or placing components, and the interior layers should be power and ground layers.
If your board will include analog signals or other signals in addition to components that operate with LVDS routing, you should consider using a 6 layer board. These other signals can run directly between your power and ground planes, and an additional ground plane can be placed directly below the back surface layer. This ensures that your interior signals will have sufficient shielding from your surface layer.
This choice of stackup is very important if you are designing a mixed signal board that uses LVDS. This type of stack offers two advantages. First, you can route LVDS signals on two sides of your board, and placing a ground plane below each signal layer provides tight coupling that helps suppress crosstalk.
Placing an additional signal layer in the interior of the board between power and ground planes will shield your analog signals from the two exterior layers, providing significant protection from EMI. Be sure to separate analog return signals from digital sections of your board in order to prevent corruption of your analog signals.
With an LVDS board for computer peripherals, there will inevitably be some kind of connector and cable that attaches to your board. This could be an edge connector (for example, with a PCIe card), or an SMT connector that connects to a cable. In both cases, you will need to allocate pins for connecting the power and ground planes in each board.
Going further, some of your components that operate with LVDS signals (some display interfaces, for example) will require split power planes that are brought to different voltages. Some components will also require that you place ground islands on your surface layers to accommodate connectors or center pads on components.
Component Layout in LVDS Boards
The list of layout guidelines for any PCB, including boards that use LVDS, is too long to list in a single article. However, we can take a look at some important guidelines that help ensure signal integrity in devices that use LVDS.
Components that operate with LVDS switch at high speeds, with signal transition times reaching sub-nanosecond levels (260 ps minimum). Therefore, many high speed design and differential pair routing rules that are applicable in other PCBs also apply in LVDS boards. However, there are some other rules that should be considered when designing LVDS PCBs.
First, as the “D” and “S” in LVDS stands for differential signalling, you will need to ensure you route these traces properly. These pairs of traces should be routed such that they maintain symmetry throughout their length. Components that are placed on pairs, e.g., resistors or coupling capacitors, should also maintain symmetry.
LVDS pairs should also be precisely length-matched to prevent undue timing skew between signals in a pair. If you examine recommendations in LVDS standards for various interfaces, you'll find different allowable skew values, which depend on the receiver's allowed skew margin. For SerDes, the recommended maximum timing skew is 30 ps, or about 1/8th of the minimum signal rise time (90%-10%). For PCIe and SATA, the tolerances drop to 1 ps (equivalent to 150 microns). This rule applies to skew between multiple differential pairs, as well as between traces in an individual differential pair.
This requirement is rather stringent, but this rule regarding skew is central to ensuring LVDS components can reject noise from environmental EMI. As LVDS components read the voltage difference between each end of the pair, any noise induced in a differential pair will be precisely subtracted at the load input.
This requirement regarding skew also creates some component placement challenges. In order to ensure traces are precisely length matched, you may be better off aligning components so that you do not need to repeatedly bend traces in a signal net. Routing directly from a transmitter to a receiver along the shortest possible path is preferred. This may be difficult, but doing this will help save board space. In addition, you can actually reduce your trace count by routing data in serial at higher data transfer rate using serializers/deserializers, allowing you to maintain high throughput.
LVDS is one of those acronyms in PCB design that might seem esoteric, but working with the right design software will help you meet basic LVDS PCB layout guidelines. Altium Designer® includes layout tools and an advanced layer stack manager, giving you full control over all aspects of your design. Best of all, these design tools are integrated with your simulation, management, and production planning tools in a single program.
Now you can download a free trial of Altium Designer. You’ll also have access to the best LVDS design features the industry demands, and all these tools are accessible within in a single interface. Talk to an Altium expert today to learn more.