Some LVDS PCB Layout Guidelines for Ensuring Signal Integrity
For me, arranging components on a PCB is like a fun puzzle. It’s something to do on a rainy day and can take the same type of trial and error approach. Working with a signaling standard like LVDS doesn’t have to be as difficult as a 1,000 piece puzzle if you know some basic design tips.
As a signaling standard used in many LCD-TVs, computer peripherals, infotainment systems, and notebook/tablet computers, designers should take some time to learn some LVDS PCB layout guidelines. If you're designing with components that use LVDS, pay attention to your these guidelines for ensuring signal integrity in your high speed PCB.
The Foundation: Understanding the LVDS Specification
Low-voltage differential signaling (LVDS) is codified in the TIA/EIA-644 standard and is a serial signaling protocol. Probably the most common electrical uses for LVDS are as an physical layer for SerDes links, long-reach channels in backplanes, or board-to-board connections. It's important to note that the TIA/EIA-644 does not define LVDS as an interface, it is a physical layer within the OSI model. In other words, this only defines a physical and electrical specification that fits within an interface standard. For example, LVDS is used as the physical layer for routing between PCIe interfaces.
The image below shows a schematic of an LVDS link; assume channel losses are 0 dB for the moment. On the left is a differential CMOS switch, which passes a 3.5 mA current onto a 100 Ohm differential pair. On the right side, the receiver reads out the differential voltage, which might be measured against some common mode DC offset. Bidirectional communication can be implemented as well in half-duplex or full duplex mode if the transceiver components can accept this, or parallel receivers and transmitters in dual simplex mode.
Physical Layer Specification
As LVDS is a physical layer specification and not a component interface specification, it only carries specific requirements in the following areas:
- Signal swing: The swing across the 100 Ohm termination resistor is 350 mV, although one should note a different impedance may be used in an LVDS link.
- Embedded clocking and encoding: LVDS does not require a specific encoding scheme, but this is allowed under the standard. 8b/10b encoding is commonly used.
- DC offset: A common DC offset in LVDS Rx/Tx components is 1.2 V.
- Topology: Single links, bi-directional links, and multidrop topology are allowed. In particular, multi-drop topology is common in backplane buses and cascaded board-to-board connections.
- Data rate: LVDS can theoretically support any data rate as long as signals are recoverable at the receiver. LVDS is typically used for serial data rates from 400 Mbps to above 3 Gbps.
- Media: Like Ethernet, LVDS is media-independent; it can be used in traces on a PCB or on cables with specified impedance.
From the above list, we see that LVDS is simply a typical high speed differential channel with flexible data rate, topology, signal swing, and rise time. As this physical layer specification is used with a range of data rates, there is no specific signal rise time; the rise time is generally less than 1 ns. With these points in mind, we have everything needed to start designing a board to work with LVDS.
LVDS PCB Layout Guidelines
Doing LVDS PCB layout successfully requires following some of the same guidelines you'd follow with other high speed signals. I'd say the only difference is in how you view losses on the board or on a cable carrying LVDS signals. The typical transmission distances ranges from several inches (chip-to-chip) to several meters for an LVDS SerDes link driving a cable between boards. On the PCB, LVDS channels have to be designed with controlled impedance but without interfering with other circuitry.
Gridding and Component Placement
LVDS links are high speed signals that are intended to have low EMI, but they can still induce crosstalk in other interconnects. Parallel LVDS links can also induce differential crosstalk in each other when switching at high speeds, so consider the spacing between differential pairs when planning your routing strategy. As with other high speed or mixed signal designs, it's a good idea to plan out a specific region of the board for LVDS channels so that they don't get too close to other circuitry.
PCB Stackup Design
Consider your PCB stackup design when planning a layout with LVDS links. Since LVDS needs impedance control, longer links will be routed on at least a 4-layer board. The two surface layers will be allocated to routing signal traces and/or placing components, and the interior layers should be power and ground layers. You can route LVDS signals on opposite sides of the board, and the internal plane layers will provide impedance control.
If you're using a wide parallel bus specification, then you'll need a lot of space for routing and you might consider leaving enough layers for impedance-controlled striplines. If you're only routing a couple LVDS links, you'll probably be fine with microstrips on a 4-layer board. Make sure to apply impedance control by setting the appropriate trace width in your routing tools.
Going further, some of your components that operate with LVDS signals (some display interfaces, for example) will require different power planes that are brought to different voltages. Some components will also require that you place ground islands on your surface layers to accommodate connectors or center pads on components. Keep these points in mind when planning the stackup and dividing up board real estate before routing.
Opt for Shorter Routing if Possible
On the PCB, LVDS routing uses low signaling swings that may need to be distinguished above a DC offset, so losses should be avoided. Long links will have greater attenuation due to dielectric losses and copper roughness/skin effect losses, which are manifested in insertion loss. Keeping links shorter ensures they see less loss compared to a longer link where insertion loss dominates. This leads to the next consideration that you won't often find in LVDS routing guidelines: how to accommodate higher signal bandwidths.
Consider the Signal Bandwidth
In shorter links, you now have the problem of return loss dominating your channels, and this will create a bandwidth limiting effect that is not normally seen in a return loss spectrum. Although it's complicated, try to design the channel to have flat impedance with closest possible matching up to the highest frequency as this will push the first return loss resonance as high as possible. For very high data rate LVDS channels, you need at least 8 GHz of bandwidth in the channel, which can be rather difficult due to dispersion in the PCB substrate and copper roughness dispersion. Take a look at this recent article on return loss to see an example of how channel bandwidth can become limited, particularly in short channels.
LVDS pairs should also be precisely length-matched to prevent undue timing skew between signals in a pair. If you examine recommendations in LVDS standards for various interfaces, you'll find different allowable skew values, which depend on the receiver's allowed skew margin. For some SerDes interfaces, you'll find maximum timing skew values of around 30 ps, or about 1/8th of the (10%-90%) rise time. For PCIe and SATA, the skew tolerances drop to an extremely low 5 mils (equivalent to 125 microns, or about 1 ps if Dk = 4).
This requirement is rather stringent, but this rule regarding skew is central to ensuring LVDS components can reject noise from environmental EMI. As LVDS components read the voltage difference between each end of the pair, any common mode noise induced in a differential pair will be precisely subtracted at the load input. If you grid out your board and placed components properly when beginning the design, you'll have left yourself enough room for length tuning structures without interfering with any other components.
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Now you can download a free trial of Altium Designer. You’ll also have access to the best LVDS design features the industry demands, and all these tools are accessible within in a single interface. Talk to an Altium expert today to learn more.