筆者について

Jeff Loyer

Signal and Power Integrity Product Manager at Altium
Jeff Loyer is the Signal and Power Integrity Product Manager at Altium. Prior to joining Altium, he spent more than 20 years as an engineer at Intel, the last 10 as signal integrity lead for their server divisions. While at Intel, he led work groups which significantly impacted the industry’s high-speed PCB design practices, including work on the Fiberweave Effect, copper roughness, environmental effects on insertion loss, and insertion loss control and measurement (inventor of SET2DIL).

最新の記事

DC Analysis of a PDN: Essential for the Digital Designer As PCBs become increasingly miniaturized, engineers are commonly faced with incorporating multiple power planes on the same layer. While this design practice introduces coupling issues, the real question is whether they can be resolved without a dedicated PDN analysis tool. Read on to find out. DC Analysis of a PDN: Essential for the Digital Designer Is there enough copper? DC analysis of a power delivery network (“PDN”), commonly referred to as 記事を読む

Is IPC-2152 Holding Your Power Integrity Back? For most designers, the Power Distribution Network (PDN) is a foreign and intimidating part of the PCB design process. But achieving optimal PDN performance is not as complicated as it seems. For many designers, the Power Distribution Network (PDN) is a foreign and intimidating part of the PCB design process. But achieving optimal PDN performance is not as complicated as it seems. In fact, the fundamental goal of optimizing your PDN can be as 記事を読む