Optical Transceiver Layout for Gigabit and Faster Ethernet

Zachariah Peterson
|  Created: August 5, 2019  |  Updated: April 27, 2020

PCB wave soldering process equipmentMind your manufacturing process during optical transceiver layout and design

The story of PCB layout and channel design for optical transceivers is really a story of high speed PCB design; it requires considering all aspects of high speed design, especially at very high data rates. Data rates reaching 400 Gbps on 10 lanes (that’s 40 Gbps per lane!) are possible over long distances with the right PCB layout and routing techniques.

Challenges in Optical Transceiver Layout and Routing

Routing between chips, or between a chip and an optical transceiver, at high networking speeds requires taking account of a number of high speed design rules, both for an individual transceiver and for the backplane that connects multiple transceivers. Some particularly important aspects of high speed design manifest themselves at very high Gbps data rates; we’ll touch on some of these aspects below. Designing a typical interconnect between a chip and a transceiver, or between two chips, as part of high speed channel design requires considering the following:

PCB Substrate Material

The substrate material determines the effective dielectric constant of the board and its loss tangent. Trace impedance increases as the substrate dielectric constant decreases, thus the geometry of a given trace needs to be modified to ensure the trace impedance takes a consistent value throughout an interconnect.

Dispersion in the substrate causes different harmonics that comprise a digital signal to move at different velocities, causing signal distortion and spreading. This increases phase jitter at the receiver. Therefore, a substrate material should be chosen with a flat dielectric constant at frequencies between the signal repetition frequency and the knee frequency. The substrate should have low losses as well. Note that it is not always feasible to satisfy both requirements simultaneously at every frequency range.

Manufacturing Considerations

At the very fast signal rise times required for high speed networking, impedance discontinuities must be minimized throughout the board. This means the use of vias should be minimized on high speed interconnects. The impedance of a given trace can vary due to variations in surface roughness and geometry, which can create signal integrity problems that contribute to jitter.

There is another aspect of surface roughness that must be addressed. At very high speeds, the inflow/outflow current in a trace will tend to settle near the edge of a copper conductor due to the skin effect, which causes resistive losses to increase. Copper conductors can be electrodeposited or pressed and rolled. The latter process tends to produce conductors with smoother surfaces, thus it is preferable in order to reduce resistive losses in an interconnect.

PCB wave soldering process equipment
Mind your manufacturing process during optical transceiver layout and design

Layer Stack

Routing guidelines for Ethernet over copper are generally implemented on 2-layer or 4-layer PCBs with power and ground islands. In Gbps-speed PCBs for optical transceivers, designation of high-speed signal layers within the stackup directly affects signal performance. Boards that include one or more BGA-mounted FPGAs generally use 6-layer or greater stackups as this provides the necessary number of signal layers for escape routing from the BGA.

Stripline routing at Gbps and faster signalling speeds is known to provide lower losses than microstrip routing and it will inevitably be used to escape a high pin density FPGA or other controller. When routed between two conductive planes, stripline traces will have some natural immunity to external EMI. However, a thicker dielectric is required to reach a given controlled impedance value, and vias must be used at the PHY, MAC, and transceiver connections. Any vias placed on such high speed interconnects should be backdrilled to prevent via stub resonance.

Jitter and Routing

The challenge in optical transceiver layout is not necessarily the data transfer rate, but rather the rise time of the converted electrical signals. This is the limiting factor that determines the impact of high speed signalling effects in any PCB. As the data rate increases, the signal rise time must decrease as well. In telecommunications, we often refer to the unit time interval (UI), which can refer to the amount of time a given symbol exists in a data stream. At 50 Gbps in a single lane, the UI is just the inverse of the data rate, or 20 ps/baud.

Jitter is just one important determinant of bit error rates, and maintaining data integrity at less than some maximum bit error rate requires keeping jitter below some allowed margin. This margin is usually expressed as a fraction of the UI; for example, a jitter margin of 0.05 UI equates to maximum jitter of 2 ps in a 25 Gbps lane (UI = 40 ps/baud). Jitter must be addressed at the chip level as it requires extremely stable driving, as well as at the PCB level with proper layout and manufacturing.

Multiple optical transceivers
Optical transceiver modules in a fiber networking switch

Crosstalk can induce jitter, thus care should be taken to prevent crosstalk between transceiver connections. Differential signalling is typically used as it provides common mode noise immunity and reduces inductive crosstalk between lanes. Placing a ground plane as close as possible to the surface layer will provide better crosstalk suppression and EMI suppression. The jitter margin will also determine limit the allowed length mismatch between each end of a differential pair. This mismatch, when combined with jitter, will cause skew to accumulate for signals travelling on an interconnect.

Given the very fast rise times used in Gbps and faster Ethernet, including for Ethernet over fiber, interconnects between the transceiver and a chip, or between two chips, must be very short or else transmission line behavior will be easily noticed and will corrupt your signals. These lines should be terminated and/or impedance matched to prevent signal reflection. With modulation schemes like 4PAM, severe signal reflection can create significant increases in BER due to the stair-step response in digital signals from repeated reflections. Impedance controlled routing is critical here as it can reduce the number of impedance matching networks required throughout the board.

The layout and simulation tools in Altium Designer are built to help you design PCBs for nearly any application. The high speed design and simulation tools are ideal for optical transceiver layout, and the data management and documentation tools can help you prepare for manufacturing.

Contact us or download a free trial if you’re interested in learning more about Altium Designer. You’ll have access to the industry’s best layout, simulation, and data management tools in a single program. Talk to an Altium expert today to learn more.

About Author

About Author

Zachariah Peterson has an extensive technical background in academia and industry. He currently provides research, design, and marketing services to companies in the electronics industry. Prior to working in the PCB industry, he taught at Portland State University and conducted research on random laser theory, materials, and stability. His background in scientific research spans topics in nanoparticle lasers, electronic and optoelectronic semiconductor devices, environmental sensors, and stochastics. His work has been published in over a dozen peer-reviewed journals and conference proceedings, and he has written 1000+ technical blogs on PCB design for a number of companies. He is a member of IEEE Photonics Society, IEEE Electronics Packaging Society, American Physical Society, and the Printed Circuit Engineering Association (PCEA), and he previously served on the INCITS Quantum Computing Technical Advisory Committee.

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